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They were sold in kits as\u000aRBK852-RBK855, with one router and 1-4 satellites.\u000a\u000aThe RBx850 are substantially similar to the RBx750 so this commit factors\u000aout a common DTS, flash script and build definition.\u000a\u000aHardware:\u000a* SoC: Qualcomm IPQ8074\u000a* RAM: 1GiB 2x Samsung 4A4G165WE-BCRC\u000a* Flash: 512MiB Winbond W29N04GZ or 256MiB Winbond W29N02GZ\u000a* WLAN 2.4GHz: QCN5024 4x4:4 b/g/n/ax\u000a* WLAN 5GHz Low Band: QCN5054 4x4:4 a/n/ac/ax 5180-5320MHz\u000a* WLAN 5GHz High Band: QCN5054 4x4:4 a/n/ac/ax 5500-5700MHz\u000a* Ethernet: 4x 1GbE LAN, 1x 2.5GbE WAN on RBR850\u000a* Serial Config: 3.3V TTL 115200-8-N-1, internal populated header\u000a* Serial Layout: Bottom <- RX, TX, GND, 3.3V (don't connect) -> Top\u000a* LEDs: green/red power, white/red/green/blue status\u000a* Buttons: 1x Reset, 1x WPS\u000a\u000aMAC addresses:\u000aLAN1: Label\u000aLAN2: Label + 1\u000aLAN3: Label + 2\u000aLAN4: Label + 3\u000aWAN: Label + 1\u000a2.4GHz: Label + 2 (RBR) or 1 (RBS)\u000a5GHz-Low: Label + 3 (RBR) or 2 (RBS)\u000a5GHz-High: Label + 4 (RBR) or 3 (RBS)\u000a\u000aFlashing Notes:\u000aThe stock firmware images are signed. Both the bootloader and the stock\u000aweb interface check the signature and will fail to boot/flash.\u000aThe bootloader automatically does NMRP when a gigabit LAN connection is\u000apresent. The stock and factory images contain a U-Boot script that is\u000aexecuted when flashing using NMRP. This is used to alter and persist the\u000aU-Boot env with a boot command that works with unsigned firmware.\u000a\u000aInstall OpenWrt:\u000a* Get the nmrpflash utility [0] and OpenWrt factory image\u000a* Find network interface to use: nmrpflash -L\u000a* Start nmrpflash: nmrpflash -i interface -f openwrt-...-factory.img\u000a* Connect one of the device LAN ports to the same network using gigabit\u000a* Plug the device in and wait for the bootloader to flash\u000a* Unplug and replug the device once the power LED on the back blinks amber\u000a\u000aRevert to Stock:\u000aThe boot command needs to be reverted before flashing the stock firmware,\u000aotherwise it will fail to boot and get stuck in recovery mode (red power\u000aLED flashing).\u000a\u000a* Still in OpenWrt run: fw_setenv bootcmd bootipq\u000a* Restart the device\u000a* Flash the stock firmware RBx850-Va.b.c.d.img using nmrpflash\u000a\u000a[0]: https://github.com/jclehner/nmrpflash\u000a\u000aAuthored by Michael Lotz.\u000a\u000aPiotr Szczepanik:\u000a* Cherry-picked the RBx850 support commit from openwrt/openwrt#22159\u000a and adapted it to current main.\u000a* Reworked the DTS networking changes for the current qualcommax\u000a ipq807x device-tree style.\u000a* Verified the RBx750 DTS split preserves the existing RBx750-specific\u000a layout while moving shared RBx750/RBx850 nodes into a common DTSI.\u000a\u000aSigned-off-by: Michael Lotz \u000aSigned-off-by: Piotr Szczepanik \u000aLink: https://github.com/openwrt/openwrt/pull/24906\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 12:23:38 +0200", "id" : "0c5547e86515d992fe7d28c6986f7f59e94fb37f", "msg" : "qualcommax: ipq807x: add Netgear RBx850 support", "paths" : [ { "editType" : "add", "file" : "target/linux/qualcommax/image/netgear_rbx750_850.bootscript" }, { "editType" : "add", "file" : "target/linux/qualcommax/dts/ipq8074-rbx750_850.dtsi" }, { "editType" : "edit", "file" : "target/linux/qualcommax/dts/ipq8074-rbx750.dtsi" }, { "editType" : "delete", "file" : "target/linux/qualcommax/image/netgear_rbx750.bootscript" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq807x/base-files/etc/board.d/02_network" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq807x/base-files/lib/upgrade/platform.sh" }, { "editType" : "add", "file" : "target/linux/qualcommax/dts/ipq8074-rbx850.dtsi" }, { "editType" : "edit", "file" : "target/linux/qualcommax/image/ipq807x.mk" }, { "editType" : "add", "file" : "target/linux/qualcommax/dts/ipq8074-rbr850.dts" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq807x/base-files/etc/hotplug.d/firmware/11-ath11k-caldata" }, { "editType" : "add", "file" : "target/linux/qualcommax/dts/ipq8074-rbs850.dts" }, { "editType" : "edit", "file" : "package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq807x" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "package/firmware/ipq-wifi/Makefile" ], "commitId" : "74eb10ed5c61feff51f8d6ca6109b94e9c504ec1", "timestamp" : 1788776618000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "ipq-wifi: update to Git HEAD (2026-08-26)\u000a\u000ac9c7cd8142ac ipq8074: add Netgear RBK850 BDF\u000a\u000aSigned-off-by: Piotr Szczepanik \u000aLink: https://github.com/openwrt/openwrt/pull/24906\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 12:23:38 +0200", "id" : "74eb10ed5c61feff51f8d6ca6109b94e9c504ec1", "msg" : "ipq-wifi: update to Git HEAD (2026-08-26)", "paths" : [ { "editType" : "edit", "file" : "package/firmware/ipq-wifi/Makefile" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "a34ff932faaab80e9ec26f2cef98e896b8d09e47", "timestamp" : 1788789548000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: fix BPDU trapping and CPU transmission\u000a\u000aThe STP APP_CTRL rule uses 0x93fc for its third word. CMD occupies\u000abits 16:15 of that word, so this selects DROP (1), not the intended\u000aREDIRECT_TO_CPU (3). Incoming BPDUs never reach the bridge protocol\u000aimplementation even though ordinary traffic continues to work.\u000a\u000aCorrecting only CMD exposes another issue: the 0x7f ingress port mask\u000aincludes CPU port 0. CPU-originated BPDUs are then trapped back to the\u000aCPU rather than transmitted to the selected external port. Exclude\u000athe CPU and SoC-specific loopback ports, deriving the remaining mask\u000afrom the port count. Use named fields for the third word so the action\u000aand port selection are explicit.\u000a\u000aOn an AX3600/IPQ8074 running 6.18.44, register readback confirmed the\u000aoriginal rule. A guarded runtime test of 0x193fc restored BPDU reception\u000abut captured locally generated BPDUs on the CPU RX path. With 0x193f4,\u000athose RX reflections disappeared and the adjacent switch received\u000abridge protocol traffic again. Reapplying that value automatically\u000aafter a reboot established RSTP with the upstream root. The patched\u000adriver also builds against the matching aarch64 kernel SDK.\u000a\u000aIPQ6018's generated mask was checked, but not tested on hardware.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: OpenAI Codex\u000aSigned-off-by: Jan Leon \u000aLink: https://github.com/openwrt/openwrt/pull/25063\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 15:59:08 +0200", "id" : "a34ff932faaab80e9ec26f2cef98e896b8d09e47", "msg" : "qualcommax: qca_ppe: fix BPDU trapping and CPU transmission", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" ], "commitId" : "7b396007440c94f8e54fd2507c813571de170be6", "timestamp" : 1788790473000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: align define values\u000a\u000aAlign all macro replacement values in qca_ppe.h with the header's dominant tab stop.\u000a\u000aThis is a whitespace-only cleanup.\u000a\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 16:14:33 +0200", "id" : "7b396007440c94f8e54fd2507c813571de170be6", "msg" : "qualcommax: qca_ppe: align define values", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/generic/pending-6.12/770-08-net-phylink-link-the-PCS-list-before-the-initial-con.patch", "target/linux/generic/pending-6.18/737-10-net-phylink-link-the-PCS-list-before-the-initial-con.patch" ], "commitId" : "77824a92b83e300962d1635dc586b74820f8fc0d", "timestamp" : 1788799060000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "generic: link the PCS list before the initial phylink config\u000a\u000aA PCS taken from the phylink PCS list is attached to its phylink instance\u000ain phylink_start(), after phylink_mac_initial_config() has already run\u000a.pcs_config() on it, so that first call sees a NULL pcs->phylink. The\u000a.mac_select_pcs() route has no such window: phylink_major_config() sets\u000apcs->phylink before it configures the PCS, which is what phylink did for\u000aevery PCS before the list existed.\u000a\u000aDSA has no .mac_select_pcs, so every DSA port whose PCS comes from a\u000apcs-handle takes the list route. pcs-qca-uniphy reads the back-reference\u000ain .pcs_config(), through phylink_expects_phy(), to tell a fixed link\u000afrom a PHY that simply does not negotiate in band, and a Zyxel NBG7815\u000apanics on the wan port as netifd brings it up:\u000a\u000a qca-ppe 3a000000.ppe wan: configuring for phy/2500base-x link mode\u000a Unable to handle kernel access to user memory outside uaccess routines\u000a at virtual address 0000000000000044\u000a pc : phylink_expects_phy+0x0/0x38\u000a lr : qca_uniphy_pcs_config_mode.isra.0+0x398/0x45c\u000a Call trace:\u000a phylink_expects_phy+0x0/0x38 (P)\u000a qca_uniphy_pcs_config+0xec/0x13c\u000a phylink_major_config+0x1e8/0x670\u000a phylink_mac_initial_config+0xb8/0x14c\u000a phylink_start+0x4c/0x280\u000a dsa_port_enable_rt+0x48/0xb0\u000a\u000aIts four psgmii ports come up first because psgmii has no in-band type at\u000aall, which short-circuits the read, and its 10g port is managed in band.\u000a\u000aLink the list where pl->pcs_state has just become PCS_STATE_STARTING, so\u000athe guarantee holds on both routes. A .pcs_change() from a PCS that is\u000anow linked earlier still resolves to nothing: phylink_run_resolve() does\u000anothing while phylink_disable_state holds PHYLINK_DISABLE_STOPPED, which\u000aonly the phylink_enable_and_run_resolve() below clears. The other two\u000aphylink_mac_initial_config() callers are unaffected, both running with\u000athe list already linked - phylink_resume() only takes that path when it\u000adid not stop, and phylink_sfp_set_config() is gated on not being stopped.\u000a\u000aThe move rides in a patch of its own rather than an edit to the imported\u000a737-02/770-02, so the imported series stays as it was taken. Both kernels\u000acarry that series and both get the patch. No 6.12 target consumes the PCS\u000alist today - the only in-tree filler lives under a files-6.18 directory\u000aand every target that would use one is on 6.18 - so nothing there is\u000abroken by the window; the two copies just have to stay the same patch.\u000a\u000aRuntime tested on a Xiaomi AX3600 (IPQ8074, QCA8075 PSGMII, kernel 6.18):\u000athe first .pcs_config() on every channel finds pcs->phylink set, at boot\u000aand again after an admin down and up, which unlinks the list in\u000aphylink_stop() and relinks it on the next start. The panic itself is not\u000areachable there, since psgmii has no in-band type and the resulting\u000aPHYLINK_PCS_NEG_NONE short-circuits the read before it happens; that arm\u000aruns on the NBG7815 in the report.\u000a\u000aFixes: 18cbd83a1443 (\"generic: 6.18: import updated standalone PCS handling\")\u000aLink: https://github.com/JuliusBairaktaris/openwrt-nss-edma/issues/23\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/24791\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 18:37:40 +0200", "id" : "77824a92b83e300962d1635dc586b74820f8fc0d", "msg" : "generic: link the PCS list before the initial phylink config", "paths" : [ { "editType" : "add", "file" : "target/linux/generic/pending-6.18/737-10-net-phylink-link-the-PCS-list-before-the-initial-con.patch" }, { "editType" : "add", "file" : "target/linux/generic/pending-6.12/770-08-net-phylink-link-the-PCS-list-before-the-initial-con.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/generic/pending-6.12/770-01-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch", "target/linux/generic/pending-6.18/737-02-net-phylink-introduce-internal-phylink-PCS-handling.patch", "target/linux/generic/pending-6.18/737-01-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch", "target/linux/generic/pending-6.12/770-02-net-phylink-introduce-internal-phylink-PCS-handling.patch", "target/linux/generic/pending-6.18/737-10-net-phylink-link-the-PCS-list-before-the-initial-con.patch", "target/linux/generic/backport-6.18/704-v7.3-net-phylink-treat-PSGMII-as-an-inband-capable-interface.patch", "target/linux/generic/pending-6.18/737-07-net-phylink-add-.pcs_link_down-PCS-OP.patch", "target/linux/generic/pending-6.12/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch", "target/linux/generic/pending-6.12/770-05-net-phylink-support-late-PCS-provider-attach.patch", "target/linux/generic/pending-6.18/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch", "target/linux/generic/pending-6.18/737-05-net-phylink-support-late-PCS-provider-attach.patch", "target/linux/generic/pending-6.12/770-03-net-phylink-add-phylink_release_pcs-to-externally-re.patch", "target/linux/generic/pending-6.18/737-03-net-phylink-add-phylink_release_pcs-to-externally-re.patch", "target/linux/generic/pending-6.12/770-08-net-phylink-link-the-PCS-list-before-the-initial-con.patch", "target/linux/generic/backport-6.12/704-v7.3-net-phylink-treat-PSGMII-as-an-inband-capable-interface.patch", "target/linux/generic/pending-6.12/770-07-net-phylink-add-.pcs_link_down-PCS-OP.patch" ], "commitId" : "2de0893dd23aae0be0eb44620e2ad271d739cd14", "timestamp" : 1788799061000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "generic: backport the phylink PSGMII in-band classification\u000a\u000aphylink_get_inband_type() omits PHY_INTERFACE_MODE_PSGMII, so\u000aphylink_pcs_neg_mode() returns early with PHYLINK_PCS_NEG_NONE for a\u000aPSGMII port, and the in-band capabilities a PCS advertises are never\u000aconsulted: qca-uniphy answers pcs_inband_caps() with\u000aLINK_INBAND_DISABLE | LINK_INBAND_ENABLE for every interface it drives,\u000aPSGMII included.\u000a\u000aBackport upstream commit 5ba017f9efef (\"net: phylink: treat PSGMII as an\u000ainband capable interface\"), which classifies PSGMII as INBAND_CISCO_SGMII\u000abeside SGMII and QSGMII and extends the generic clause 22 PCS helpers to\u000amatch, to both kernel copies the tree carries.\u000a\u000aNo board in the tree declares managed = \"in-band-status\" on a PSGMII\u000aport, so every PSGMII port moves from PHYLINK_PCS_NEG_NONE to\u000aPHYLINK_PCS_NEG_OUTBAND, PHY-managed and fixed links alike. A PCS\u000adriver can distinguish the two with phylink_expects_phy() and force\u000aits channel only on a fixed link.\u000a\u000aThe 6.12 copy adapts the phylink_mii_c22_pcs_decode_state() hunk, whose\u000aSGMII case carries no neg_mode guard on that kernel.\u000a\u000aExercised on a Xiaomi AX3600 (IPQ8074, kernel 6.18), whose four ports are\u000aPSGMII channels of one UNIPHY. With two of them declared as fixed links,\u000athe channel force bit the qca-uniphy PCS drives reads 0 without this\u000apatch and 1 with it, the channel speed field following the declared\u000aspeed, while the two channels still behind a PHY are untouched either\u000away. On the unmodified device tree nothing changes: every port links as\u000abefore and every channel register reads the value it held.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/24791\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 18:37:41 +0200", "id" : "2de0893dd23aae0be0eb44620e2ad271d739cd14", "msg" : "generic: backport the phylink PSGMII in-band classification", "paths" : [ { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-05-net-phylink-support-late-PCS-provider-attach.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/706-net-phy-populate-host_interfaces-when-attaching-PHY.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-03-net-phylink-add-phylink_release_pcs-to-externally-re.patch" }, { "editType" : "add", "file" : "target/linux/generic/backport-6.18/704-v7.3-net-phylink-treat-PSGMII-as-an-inband-capable-interface.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-07-net-phylink-add-.pcs_link_down-PCS-OP.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-08-net-phylink-link-the-PCS-list-before-the-initial-con.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-07-net-phylink-add-.pcs_link_down-PCS-OP.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-10-net-phylink-link-the-PCS-list-before-the-initial-con.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-02-net-phylink-introduce-internal-phylink-PCS-handling.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-01-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-05-net-phylink-support-late-PCS-provider-attach.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-03-net-phylink-add-phylink_release_pcs-to-externally-re.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.12/770-01-net-phylink-keep-and-use-MAC-supported_interfaces-in.patch" }, { "editType" : "add", "file" : "target/linux/generic/backport-6.12/704-v7.3-net-phylink-treat-PSGMII-as-an-inband-capable-interface.patch" }, { "editType" : "edit", "file" : "target/linux/generic/pending-6.18/737-02-net-phylink-introduce-internal-phylink-PCS-handling.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/pcs/pcs-qca-uniphy.c", "target/linux/qualcommax/files/include/linux/pcs/pcs-qca-uniphy.h" ], "commitId" : "29c5542cd65f6ef8997090e0cf1e88129105d646", "timestamp" : 1788799061000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: pcs: qca-uniphy: force the channel on every UNIPHY\u000a\u000aA fixed link carries no in-band negotiation, so the UNIPHY channel has to\u000abe told to take its speed from the channel register instead of waiting\u000afor a word that never arrives. The driver does that only on IPQ5018 and\u000aleaves a TODO for the other two SoCs.\u000a\u000aThere is nothing to work out for them: the SSDK writes the same bit on\u000aall three. Its IPQ5018 path, adpt_mp_uniphy_mode_ctrl_set(), writes\u000anewaddedfromhere_ch0_force_speed_25m through\u000ahppe_uniphy_channel0_input_output_4_set(), and its IPQ6018/IPQ8074 path,\u000a__adpt_hppe_uniphy_sgmii_mode_set(), writes the same field through\u000ahppe_uniphy_channel0_force_speed_mode_set(), a wrapper around that same\u000aaccessor - UNIPHY_CH_CTRL bit 3, at the same offset on every generation.\u000aThe vendor condition, PHY_F_FORCE, comes from the port's forced-speed and\u000aforced-duplex DT properties, which is a fixed link: what phylink reports\u000aas an outband neg_mode with no PHY expected.\u000a\u000aDrop the SoC test, and clear the bit for a port that is not a fixed link\u000aas the vendor does, so a channel cannot keep a force left from an earlier\u000amode. The same function also serves USXGMII and 10GBASE-R, where the XPCS\u000adrives the channel and UNIPHY_CH_CTRL is not the register in play - the\u000aSSDK writes the bit only from its SGMII mode sets - so neither write is\u000amade in those modes.\u000a\u000aA forced channel then reads its speed from the SPEED_MODE field next to\u000athat bit, which nothing ever wrote - the SSDK has an accessor for it and\u000ano caller. It kept its 1000 Mbps reset value while pcs_link_up() moved\u000aonly the RX and TX clock rates, so a fixed link at 10 or 100 Mbps drove\u000athe channel at the wrong speed. Program the field from the speed\u000apcs_link_up() is handed, in the encoding the receive path already decodes\u000aout of the status register, and only for a channel the same predicate\u000areports as forced: an in-band channel carries its speed in the negotiated\u000aword and leaves the field unread. 2500BASE-X has no encoding of its own -\u000aSGMII+ carries the rate in the mode - and keeps the 1000 value the vendor\u000aleaves there.\u000a\u000aExercised on a Xiaomi AX3600 (IPQ8074, kernel 6.18), whose four ports\u000ashare UNIPHY0. Behind a QCA8075 the clear leaves FORCE_MODE at 0 and\u000aSPEED_MODE at its 1000 reset value, and a port linked at 100 Mbps holds\u000athat value while its UNIPHY port clock follows the link down to 25 MHz,\u000aso pcs_link_up() runs for the lower speed and leaves the field to the\u000ain-band word. Channels of the same instance declared as fixed links read\u000aback FORCE_MODE set with SPEED_MODE following the declared speed - 0 at\u000a10 Mbps, 1 at 100 and 2 at 1000 - and the channels still behind a PHY\u000aunchanged. The eleven IPQ5018 boards with a fixed link on a UNIPHY all\u000adeclare 1000 Mbps, the value the field already holds, so the speed half\u000ais a latent defect there rather than a visible one, and no IPQ6018 or\u000aIPQ8074 board in the tree has a fixed link on a UNIPHY at all.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/24791\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 18:37:41 +0200", "id" : "29c5542cd65f6ef8997090e0cf1e88129105d646", "msg" : "qualcommax: pcs: qca-uniphy: force the channel on every UNIPHY", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/pcs/pcs-qca-uniphy.c" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/include/linux/pcs/pcs-qca-uniphy.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/dts/ipq8072-301w.dts" ], "commitId" : "3b35c7074a2d08bb55fa009699962b3726aea6c4", "timestamp" : 1788800549000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: ipq807x: 301w: read the port MAC addresses from ART\u000a\u000aThe board names its six ports through ethernetN aliases for the bootloader\u000ato patch an address into, and since the PPE conversion only the first two\u000aarrive. On r35301-d47ce71a89, the last snapshot before it, every port came\u000aup on an address of its own; on r35323-7ff96bf05c, the first one after,\u000alan1, lan2, 10g-1 and 10g-2 have none and inherit the conduit's, so four\u000aports and the bridge above them all answer to one MAC.\u000a\u000aThe addresses the bootloader hands out come from the MAC table at the start\u000aof 0:art, one 6-byte slot per ethernetN alias. Describe those slots, so the\u000aports can read them whatever the bootloader does. ipq8071-ax3600.dtsi\u000adescribes its own ART table the same way.\u000a\u000aThe mapping is confirmed on a 301w: the table holds 24:5e:be:55:69:32\u000athrough :37 in slots 0 to 5 and nothing else, and the pre-conversion\u000asnapshot brought up each port on the slot its alias names - lan4 on :32,\u000alan3 :33, lan2 :34, lan1 :35, 10g-1 :36, 10g-2 :37.\u000a\u000aof_get_mac_address() consults the DT properties before the nvmem cell, so\u000aa port the bootloader patched keeps the address it has.\u000a\u000aFixes: f50435627d37 (\"qualcommax: ipq60xx/ipq807x: convert to PPE networking stack\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/24528\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-07 19:02:29 +0200", "id" : "3b35c7074a2d08bb55fa009699962b3726aea6c4", "msg" : "qualcommax: ipq807x: 301w: read the port MAC addresses from ART", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/dts/ipq8072-301w.dts" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/patches-6.18/197-arm64-dts-mediatek-mt7986-correct-timer-frequency.patch" ], "commitId" : "f36067d4e9c2e2a71b466a19ce4211e4d4a39228", "timestamp" : 1788819753000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/daniel", "fullName" : "daniel" }, "authorEmail" : "daniel@makrotopia.org", "comment" : "mediatek: correct MT7986 system timer rate\u000a\u000aPort MediaTek commit 6a4c41c41410 (\"fix timer inaccurate\"), which\u000acorrects the architected timer rate from 13 MHz to 12,986,200 Hz in the\u000aDTS files for both MT7986A and MT7986B.\u000a\u000aUpstream mt7986b.dtsi includes mt7986a.dtsi, so add the corrected rate\u000aonce to the common timer node. This makes the architected timer driver\u000aoverride the 13 MHz value reported by firmware through CNTFRQ_EL0 for\u000aboth SoC variants.\u000a\u000aThe resulting 1062 ppm discrepancy exceeds the kernel's 500 ppm NTP\u000acorrection limit. This matches reports of sysntpd remaining saturated at\u000a+500 ppm on the GL-MT6000.\u000a\u000aLink: https://github.com/mediatek/mtk-openwrt-feeds/commit/6a4c41c41410cd5042ad10c39da6593ba036283c\u000aLink: https://github.com/openwrt/openwrt/issues/24789\u000aSigned-off-by: Andrea Pesaresi \u000a", "date" : "2026-09-07 23:22:33 +0100", "id" : "f36067d4e9c2e2a71b466a19ce4211e4d4a39228", "msg" : "mediatek: correct MT7986 system timer rate", "paths" : [ { "editType" : "add", "file" : "target/linux/mediatek/patches-6.18/197-arm64-dts-mediatek-mt7986-correct-timer-frequency.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/econet/patches-6.18/044-16-v7.3-pinctrl-airoha-fix-edge-triggered-interrupts-han.patch", "target/linux/econet/patches-6.18/044-06-v7.3-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN758.patch", "target/linux/econet/patches-6.18/044-18-v7.3-pinctrl-airoha-statically-allocate-gpio-regs-str.patch", "target/linux/econet/patches-6.18/044-19-v7.3-pinctrl-airoha-move-common-definitions-to-the-se.patch", "target/linux/econet/patches-6.18/044-21-v7.3-pinctrl-airoha-an7581-remove-en7581-prefix-from-.patch", "target/linux/econet/patches-6.18/044-23-v7.3-pinctrl-airoha-an7583-rename-registers-to-match-.patch", "target/linux/econet/patches-6.18/042-03-v6.19-pinctrl-airoha-add-support-for-Airoha-AN7583-PINs.patch", "target/linux/econet/patches-6.18/044-12-v7.3-pinctrl-airoha-minor-improvements.patch", "target/linux/econet/patches-6.18/043-09-v7.2-pinctrl-airoha-an7583-add-missed-gpio22-pin-group.patch", "target/linux/econet/patches-6.18/044-07-v7.3-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch", "target/linux/econet/patches-6.18/043-05-v7.2-pinctrl-airoha-an7581-fix-incorrect-led-mapping-in-p.patch", "target/linux/econet/patches-6.18/043-04-v7.2-pinctrl-airoha-an7583-fix-misprint-in-gpio19-pinconf.patch", "target/linux/econet/patches-6.18/044-28-v7.3-pinctrl-airoha-try-to-find-chip-scu-node-by-phan.patch", "target/linux/econet/patches-6.18/044-02-v7.3-pinctrl-airoha-an7581-fix-pinconf-of-i2c_scl-i2c.patch", "target/linux/econet/patches-6.18/044-11-v7.3-pinctrl-airoha-add-set_direction-helper-for-gpio.patch", "target/linux/econet/patches-6.18/044-13-v7.3-pinctrl-airoha-fix-getting-gpiochip-pinctrl-poin.patch", "target/linux/econet/patches-6.18/044-22-v7.3-pinctrl-airoha-an7583-remove-an7583-prefix-from-.patch", "target/linux/econet/patches-6.18/043-10-v7.2-pinctrl-airoha-an7583-fix-phy1_led1-pin-function.patch", "target/linux/econet/patches-6.18/043-11-v7.2-pinctrl-airoha-an7583-remove-undefined-groups-from-p.patch", "target/linux/econet/patches-6.18/042-01-v6.19-pinctrl-airoha-convert-PHY-LED-GPIO-to-macro.patch", "target/linux/econet/patches-6.18/044-15-v7.3-pinctrl-airoha-fix-IRQ-mask-unmask-code.patch", "target/linux/econet/patches-6.18/044-24-v7.3-pinctrl-airoha-an7583-add-support-for-npu_uart-p.patch", "target/linux/econet/patches-6.18/043-01-v7.2-pinctrl-airoha-Fix-type-in-.pin_config_group_get-cal.patch", "target/linux/econet/patches-6.18/044-05-v7.3-pinctrl-airoha-an7583-fix-muxing-of-non-gpio-def.patch", "target/linux/econet/patches-6.18/043-03-v7.2-pinctrl-airoha-an7583-add-missed-gpio32-pin-group.patch", "target/linux/econet/patches-6.18/044-20-v7.3-pinctrl-airoha-split-driver-on-shared-code-and-S.patch", "target/linux/econet/patches-6.18/044-10-v7.3-pinctrl-airoha-add-missed-get_direction-function.patch", "target/linux/econet/patches-6.18/043-07-v7.2-pinctrl-airoha-fix-pwm-pin-function-for-an7581-and-a.patch", "target/linux/econet/patches-6.18/044-04-v7.3-pinctrl-airoha-an7581-fix-mux-conf-of-pcie_reset.patch", "target/linux/econet/patches-6.18/044-14-v7.3-pinctrl-airoha-add-missed-IRQ-resource-helpers.patch", "target/linux/econet/patches-6.18/043-02-v7.2-pinctrl-Move-Airoha-driver-to-dedicated-directory.patch", "target/linux/econet/patches-6.18/044-25-v7.3-pinctrl-airoha-an7583-add-support-for-pon_alt-pi.patch", "target/linux/econet/patches-6.18/042-04-v6.19-pinctrl-airoha-Fix-AIROHA_PINCTRL_CONFS_DRIVE_E2.patch", "target/linux/econet/patches-6.18/043-06-v7.2-pinctrl-airoha-an7583-fix-incorrect-led-mapping-in-p.patch", "target/linux/econet/patches-6.18/044-26-v7.3-pinctrl-airoha-an7583-add-support-for-olt-pinmux.patch", "target/linux/econet/patches-6.18/044-08-v7.3-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch", "target/linux/econet/patches-6.18/044-27-v7.3-pinctrl-airoha-add-support-of-en7523-SoC.patch", "target/linux/econet/patches-6.18/044-03-v7.3-pinctrl-airoha-an7583-fix-I2C0_SDA_PD-register-b.patch", "target/linux/econet/patches-6.18/043-08-v7.2-pinctrl-airoha-an7583-fix-gpio21-pin-group.patch", "target/linux/econet/patches-6.18/044-17-v7.3-pinctrl-airoha-remove-not-needed-irq_type-array.patch", "target/linux/econet/patches-6.18/044-01-v7.3-pinctrl-airoha-fix-mdio-bitfield-names.patch", "target/linux/econet/patches-6.18/042-02-v6.19-pinctrl-airoha-convert-PWM-GPIO-to-macro.patch", "target/linux/econet/patches-6.18/044-09-v7.3-pinctrl-airoha-an7583-fix-spi-group-pins.patch", "target/linux/econet/patches-6.18/042-05-v6.19-pinctrl-airoha-convert-comma-to-semicolon.patch" ], "commitId" : "43073ac09b0767eab4816fe1c5db0e39fdfc985e", "timestamp" : 1788853893000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "econet: copy Airoha pinctrl backports from the airoha target\u000a\u000aThe EN7528 pin controller support that follows needs the Airoha pinctrl\u000adriver in its v7.3 shape: moved out of drivers/pinctrl/mediatek into its\u000aown directory and split into shared code plus per-SoC drivers.\u000a\u000aThe airoha target already carries that whole chain for 6.18, so copy the\u000apatches from there.\u000a\u000aNo functional change.\u000a\u000aSigned-off-by: Ahmed Naseef \u000aLink: https://github.com/openwrt/openwrt/pull/25013\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-08 09:51:33 +0200", "id" : "43073ac09b0767eab4816fe1c5db0e39fdfc985e", "msg" : "econet: copy Airoha pinctrl backports from the airoha target", "paths" : [ { "editType" : "add", "file" : "target/linux/econet/patches-6.18/044-22-v7.3-pinctrl-airoha-an7583-remove-an7583-prefix-from-.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/042-05-v6.19-pinctrl-airoha-convert-comma-to-semicolon.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/043-05-v7.2-pinctrl-airoha-an7581-fix-incorrect-led-mapping-in-p.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/042-02-v6.19-pinctrl-airoha-convert-PWM-GPIO-to-macro.patch" }, { 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"target/linux/econet/patches-6.18/044-09-v7.3-pinctrl-airoha-an7583-fix-spi-group-pins.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/043-08-v7.2-pinctrl-airoha-an7583-fix-gpio21-pin-group.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/044-06-v7.3-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN758.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/044-18-v7.3-pinctrl-airoha-statically-allocate-gpio-regs-str.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/043-01-v7.2-pinctrl-airoha-Fix-type-in-.pin_config_group_get-cal.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/043-10-v7.2-pinctrl-airoha-an7583-fix-phy1_led1-pin-function.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/044-12-v7.3-pinctrl-airoha-minor-improvements.patch" }, { "editType" : "add", "file" : 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"target/linux/econet/dts/en7528_dasan_h660gm-a-airtel.dts", "target/linux/econet/patches-6.18/102-pinctrl-airoha-fix-setting-of-GPIO-direction.patch", "target/linux/econet/patches-6.18/044-29-v7.3-pinctrl-airoha-add-support-of-an7563-SoC.patch", "target/linux/econet/dts/en7528_jiofiber_jcow407.dts", "target/linux/econet/en7528/config-6.18", "target/linux/econet/dts/en7528_dasan_h660gm-a.dtsi", "target/linux/econet/patches-6.18/045-03-v7.4-pinctrl-airoha-add-support-of-en7528-SoC.patch", "target/linux/econet/dts/en7528_jiofiber_jcow414.dts", "target/linux/econet/patches-6.18/045-02-v7.4-dt-bindings-pinctrl-Add-EcoNet-EN7528-pin-contro.patch" ], "commitId" : "23aaf320ade912fc128070f562182a4c380718ec", "timestamp" : 1788853894000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "econet: en7528: add pin controller support\u000a\u000aBackport the EN7528 pin controller, accepted upstream for v7.4:\u000a\u000a pinctrl: airoha: limit GPIO interrupts to interrupt-capable pins\u000a dt-bindings: pinctrl: Add EcoNet EN7528 pin controller\u000a pinctrl: airoha: add support of en7528 SoC\u000a\u000aThe AN7563 driver from v7.3 comes along because the first of those\u000atouches it, and a not yet upstream fix for the GPIO direction bits is\u000aadded on top. That one clears both bits of the two bit GPIO_CTRL field\u000ainstead of only the LSB, so a bootloader leaving the reserved value\u000abehind no longer keeps the pin from driving.\u000a\u000aOnly GPIO0-GPIO15 are wired to the interrupt controller, and\u000agpiod_to_irq() now fails for the others rather than handing out an\u000ainterrupt that can never fire. Split the buttons accordingly: those\u000abelow GPIO16 become interrupt driven gpio-keys, the rest stay in a\u000agpio-keys-polled node.\u000a\u000aSigned-off-by: Ahmed Naseef \u000aLink: https://github.com/openwrt/openwrt/pull/25013\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-08 09:51:34 +0200", "id" : "23aaf320ade912fc128070f562182a4c380718ec", "msg" : "econet: en7528: add pin controller support", "paths" : [ { "editType" : "add", "file" : "target/linux/econet/patches-6.18/102-pinctrl-airoha-fix-setting-of-GPIO-direction.patch" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/045-02-v7.4-dt-bindings-pinctrl-Add-EcoNet-EN7528-pin-contro.patch" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber_jcow407.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528.dtsi" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a-airtel.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a-generic.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber.dtsi" }, { "editType" : "edit", "file" : "target/linux/econet/en7528/config-6.18" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/044-29-v7.3-pinctrl-airoha-add-support-of-an7563-SoC.patch" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber_jcow414.dts" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/045-01-v7.4-pinctrl-airoha-limit-GPIO-interrupts-to-interrup.patch" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a.dtsi" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/045-03-v7.4-pinctrl-airoha-add-support-of-en7528-SoC.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "tools/erofs-utils/Makefile" ], "commitId" : "f3f427048a8828f61270add14a113d70610d09b2", "timestamp" : 1788854974000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "tools: erofs-utils: update to 1.9.4\u000a\u000aChangeLog:\u000a https://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs-utils.git/tree/ChangeLog?h=v1.9.4\u000a\u000aBuild system: x86/64\u000aTested on: x86/64\u000a\u000aSigned-off-by: Andy Chiang \u000aLink: https://github.com/openwrt/openwrt/pull/24991\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-08 10:09:34 +0200", "id" : "f3f427048a8828f61270add14a113d70610d09b2", "msg" : "tools: erofs-utils: update to 1.9.4", "paths" : [ { "editType" : "edit", "file" : "tools/erofs-utils/Makefile" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq5018.c" ], "commitId" : "098e599864fa070916d2f6c39e6f2ec8b0173c62", "timestamp" : 1788857775000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: ipq50xx: add 1000Base-X for Qualcomm IPQ5018 DWMAC driver\u000a\u000a1000Base-X is supported by UNIPHY but missing from IPQ5018 DWMAC driver.\u000aAdd it back.\u000a\u000aVerified with YT9215.\u000a\u000aSigned-off-by: David Yang \u000aLink: https://github.com/openwrt/openwrt/pull/25052\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-08 10:56:15 +0200", "id" : "098e599864fa070916d2f6c39e6f2ec8b0173c62", "msg" : "qualcommax: ipq50xx: add 1000Base-X for Qualcomm IPQ5018 DWMAC driver", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq5018.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_scheduler.c" ], "commitId" : "73c6d07df9bb37a5775d73920cadab4fb56eec5c", "timestamp" : 1788872589000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: fix CPPE BM TDM schedule\u000a\u000aThe CPPE buffer manager TDM table contains 98 entries, while the\u000aSSDK cppe_port_tdm0_tbl has 96. The first 96 entries match exactly; the\u000atrailing CPU ingress and egress pair duplicates the beginning of the\u000acircular schedule and makes ARRAY_SIZE program a depth of 98.\u000a\u000aDrop the duplicate pair so the schedule and depth match SSDK.\u000a\u000aLink: https://github.com/openwrt/openwrt/pull/24203#issuecomment-5446469623\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-08 15:03:09 +0200", "id" : "73c6d07df9bb37a5775d73920cadab4fb56eec5c", "msg" : "qualcommax: qca_ppe: fix CPPE BM TDM schedule", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_scheduler.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/generic/files/drivers/platform/mikrotik/Kconfig", "target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c" ], "commitId" : "7161fa5814480304b5a3143d0549735cff26ca06", "timestamp" : 1788884449000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "generic: mikrotik: expose preboot etherboot settings in rb_softconfig\u000a\u000aRouterBOOT can be told to look for a netboot server for a few seconds\u000abefore falling through to the configured boot device, optionally\u000arestricted to a single Netinstall server. RouterOS calls these\u000apreboot-etherboot and preboot-etherboot-server. Neither was modelled\u000ahere, so on a board running Linux rather than RouterOS they could not be\u000aread or changed at all.\u000a\u000aThat matters most on a board where Linux has replaced RouterOS: without\u000athese, the only way to arrange a netboot is boot_device=ethonce, which\u000ais one-shot and must be rewritten before every attempt. preboot-etherboot\u000ais persistent, needs no write per boot, and still falls through to the\u000aboot device when no server answers.\u000a\u000aAdd both:\u000a\u000a preboot_etherboot tag 0x24, 0..30 seconds, zero disabling the wait\u000a preboot_etherboot_server tag 0x25, an IPv4 address, 0.0.0.0 for any\u000a\u000aRouterBOOT has no interactive presentation of either setting to mimic:\u000aneither appears in its setup menu, and both can only be written from\u000aRouterOS. Rather than borrow the \"disabled\" and \"any\" keywords RouterOS\u000auses for zero, present both tags as they are stored. RouterOS rejects a\u000atimeout of 31, which is where the upper bound comes from.\u000a\u000aNote the server address is stored in network byte order, unlike every\u000aother tag in this record, which is a little-endian u32. 192.168.1.142 is\u000aheld as c0 a8 01 8e, so reading it as a u32 would yield 142.1.168.192 -\u000aa valid-looking address pointing at a different host.\u000a\u000aVerified on a MikroTik E50UG (hEX refresh):\u000a\u000a - the show path decodes a server address written by RouterOS 7.24.2\u000a - a write of 10.20.30.40 lands in flash as 0a 14 1e 28\u000a - out-of-range timeouts and malformed addresses are rejected\u000a - with preboot_etherboot set to 5 from Linux and boot_device left at\u000a flasheth, RouterBOOT netboots; set back to zero, it boots from NAND\u000a\u000aBoth tag numbers were confirmed by diffing the soft_config record before\u000aand after changing each setting from RouterOS. They have not been\u000across-checked against other MikroTik hardware.\u000a\u000aSigned-off-by: Matt Eaton \u000aLink: https://github.com/openwrt/openwrt/pull/25044\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-08 18:20:49 +0200", "id" : "7161fa5814480304b5a3143d0549735cff26ca06", "msg" : "generic: mikrotik: expose preboot etherboot settings in rb_softconfig", "paths" : [ { "editType" : "edit", "file" : "target/linux/generic/files/drivers/platform/mikrotik/Kconfig" }, { "editType" : "edit", "file" : "target/linux/generic/files/drivers/platform/mikrotik/rb_softconfig.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "package/network/services/dnsmasq/Makefile", "package/network/services/dnsmasq/files/dnsmasq.init" ], "commitId" : "acde2ff93ec1c2d234011ae246e3a0f1038cd2ec", "timestamp" : 1788885320000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "dnsmasq: add bare hostname for static leases\u000a\u000aStatic DHCP entries with dns enabled only had\u000atheir FQDN written to the generated hosts file, so\u000athe bare hostname would not resolve unless the host also had\u000aan active DHCP lease:\u000a\u000a $ dig +short dockbox-vm\u000a $ dig +short dockbox-vm.lan\u000a 10.100.1.20\u000a\u000aSigned-off-by: Tucker Kern \u000aLink: https://github.com/openwrt/openwrt/pull/25012\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-08 18:35:20 +0200", "id" : "acde2ff93ec1c2d234011ae246e3a0f1038cd2ec", "msg" : "dnsmasq: add bare hostname for static leases", "paths" : [ { "editType" : "edit", "file" : "package/network/services/dnsmasq/files/dnsmasq.init" }, { "editType" : "edit", "file" : "package/network/services/dnsmasq/Makefile" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" ], "commitId" : "918c72d210a977e6965491cde3b75a6cc309844a", "timestamp" : 1788888628000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl930x: mask the PIE action VID/act fields before shifting\u000a\u000artl930x_write_pie_action() built the ivid_act, ivid_data and ovid_act\u000afields of the PIE action with the mask applied *after* the shift:\u000a\u000a\u0009r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;\u000a\u000aso only the low three bits of a 12-bit assigned VID survived - e.g. an\u000a\"action vlan push id 100\" was programmed as VID 4, id 254 as VID 6 -\u000awhile ivid_act / ovid_act were masked to zero and never took effect.\u000aovid_data was already done the right way round.\u000a\u000aMask each field to its width and then shift it into place, matching\u000aovid_data and the rest of the function.\u000a\u000aVerified on an RTL9300 (Zyxel XGS1210-12): with an ingress cls_flower\u000arule carrying \"action vlan push id \", the PIE action now encodes the\u000arequested VID (100 / 254 / 4094 read back exactly from r[15], where the\u000aold code produced 4 / 6 / 6), and a matching frame leaves the CPU port\u000atagged with that VID (confirmed by tcpdump against a no-rule control).\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25070\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 19:30:28 +0200", "id" : "918c72d210a977e6965491cde3b75a6cc309844a", "msg" : "realtek: dsa: rtl930x: mask the PIE action VID/act fields before shifting", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "3c17984e3a7fc6a9cf516090f7a52f10f6152143", "timestamp" : 1788888628000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: rework packet counter alloc, add a free helper\u000a\u000artl83xx_packet_cntr_alloc() had no counterpart: the L3 route path\u000aopen-codes the release as a bare set_bit() on packet_cntr_use_bm, which\u000aonly frees the 32-bit half and leaves the enclosing 64-bit octet block\u000amarked used forever.\u000a\u000aRename it to rtldsa_packet_cntr_alloc() (rtldsa_ prefix convention),\u000abound the bitmap scans by n_counters, take reg_mutex with scoped_guard()\u000aand use the non-atomic __*_bit() ops now that it all runs under the lock,\u000aand add rtldsa_packet_cntr_free(): it ignores a double release, marks the\u000acounter free and, once both halves of its octet block are free, returns\u000athe block to the octet pool.\u000a\u000aSwitch the L3 route teardown to the helper; no functional change there\u000abeyond also releasing the octet block.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25070\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 19:30:28 +0200", "id" : "3c17984e3a7fc6a9cf516090f7a52f10f6152143", "msg" : "realtek: dsa: rtl83xx: rework packet counter alloc, add a free helper", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "c3007f24a6bc10e15612fb51fb74e52f315180a9", "timestamp" : 1788888628000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: fix rtl83xx_configure_flower() error unwinding\u000a\u000aOn any failure after the flow was inserted into the hashtable\u000artl83xx_configure_flower() returned straight away, leaking the flow and\u000aleaving a dangling entry in tc_ht. The RCU section around the duplicate\u000alookup also used a goto label for no reason.\u000a\u000aDrop the RCU reference right after the lookup, and unwind through\u000aout_remove / out_free so a failed rtl83xx_add_flow() or pie_rule_add()\u000aremoves the entry and frees the flow. Also propagate rtl83xx_add_flow()'s\u000areturn value, which was previously ignored, and log the insert failure\u000awith dev_err().\u000a\u000apie_rule_add() can fail after rtldsa_packet_cntr_alloc() has handed out a\u000apacket counter, so release it with rtldsa_packet_cntr_free() from the\u000aout_remove path. kzalloc() leaves rule.packet_cntr at 0, a valid counter\u000aid, so initialise it to -1 and let the helper skip a negative id.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25070\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 19:30:28 +0200", "id" : "c3007f24a6bc10e15612fb51fb74e52f315180a9", "msg" : "realtek: dsa: rtl83xx: fix rtl83xx_configure_flower() error unwinding", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "9d3500939a7bb390c641f2a6cc0a9435e5648a3f", "timestamp" : 1788888629000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: validate tc flower match keys and actions\u000a\u000artl83xx_parse_flow_rule() accepted whatever it was handed: unknown\u000adissector keys were ignored, partial EtherType / ip_proto / VLAN masks\u000awere treated as exact, the ip_proto decoding set frame_type_l4 twice for\u000aTCP and never for a UDP-only match, and its return value was dropped with\u000aa \"TODO: check error\".\u000a\u000aReject what the PIE cannot express before programming it:\u000a\u000a - fail on dissector keys outside the supported set, and on a rule\u000a combining IPv4 and IPv6 addresses;\u000a - require a full 0xffff EtherType mask and a full 0xff ip_proto mask,\u000a decode ip_proto through a switch (adding IGMP), and bail on anything\u000a else;\u000a - reject VLAN priority / DEI / ethertype sub-matches, and a VLAN TPID\u000a other than 802.1Q (cls_flower always sets a full vlan_tpid mask, so\u000a an unconditional reject would kill the VLAN match arm);\u000a - add rtldsa_validate_flow_actions() to accept only drop / trap /\u000a redirect / mirred - FLOW_ACTION_VLAN_PUSH / _POP included in the\u000a rejection, the ivid / ovid PIE translation in rtl83xx_add_flow() is\u000a neither programmed nor tested through this offload - honour control\u000a flags and the hw-stats type, and propagate the parse and action\u000a errors out of rtl83xx_add_flow().\u000a\u000aUnknown EtherTypes are rejected here; generic EtherType matching arrives\u000awith the cls_flower offload series (openwrt/openwrt#24994), which rebases\u000aon top of this.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25070\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 19:30:29 +0200", "id" : "9d3500939a7bb390c641f2a6cc0a9435e5648a3f", "msg" : "realtek: dsa: rtl83xx: validate tc flower match keys and actions", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" ], "commitId" : "870c10eb8f8cfaa41960438290aaa637e5fb6562", "timestamp" : 1788891538000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: drop an unused read in the LAG track map\u000a\u000artldsa_930x_lag_set_port2group() and rtldsa_931x_lag_set_port2group()\u000aread the SRC_TRK_MAP entry before writing it, but neither looks at what\u000acame back, and the entry is one register wide on both SoCs, so the\u000awrite that follows replaces all of it.\u000a\u000aThe width is Realtek's own: the GPL SDK table lists give SRC_TRK_MAP as\u000aaccess type 8 with one data register on RTL9300, and type 13 with one\u000adata register on RTL9310 (src/hal/chipdef/longan/rtk_longan_table_list.c\u000aand .../mango/rtk_mango_table_list.c).\u000a\u000aThe value written is unchanged; what goes is one table transaction per\u000aaffected port, since the caller walks every port a membership change\u000atouches.\u000a\u000aCompile-tested on realtek/rtl930x. Not run on hardware.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25062\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 20:18:58 +0200", "id" : "870c10eb8f8cfaa41960438290aaa637e5fb6562", "msg" : "realtek: dsa: drop an unused read in the LAG track map", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/Makefile", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c" ], "commitId" : "11ee1eed06a2c4326709e424b606aaa8a283a0cf", "timestamp" : 1788891538000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: table: separate table access from DSA\u000a\u000aThe Otto SoCs reach most of their switch state through indirect table\u000aaccess: a command word carrying table, index and direction goes into\u000aone register, and the entry itself appears in a window of data\u000aregisters. That mechanism is not layer 2 and has no natural home in a\u000aDSA driver; it sits in common.c only because DSA happens to be its\u000afirst consumer.\u000a\u000aMove the descriptor array, struct table_reg and the rtl_table_*\u000afunctions verbatim into table.c and table.h. Nothing is renamed and no\u000aline of the implementation changes; rtl-otto.h includes the new header,\u000aso every consumer compiles unchanged.\u000a\u000aThe consumers already called these symbols externally, so relocating\u000athe definitions only moves them from common.o to table.o. Built for\u000arealtek/rtl930x before and after: rtl838x.o, rtl839x.o, rtl930x.o,\u000artl931x.o and l3.o are identical once debug sections are stripped, and\u000acommon.o loses 1536 bytes of code and data, 1004 of text and 532 of\u000adata. The raw objects do differ,\u000abecause CONFIG_DEBUG_INFO records line numbers from rtl-otto.h.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25062\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 20:18:58 +0200", "id" : "11ee1eed06a2c4326709e424b606aaa8a283a0cf", "msg" : "realtek: table: separate table access from DSA", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" }, { "editType" : "add", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/Makefile" }, { "editType" : "add", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" ], "commitId" : "9f62ca8ff14d701928b425b53d0093de80eb0df6", "timestamp" : 1788891538000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: table: read and write whole table entries\u000a\u000aTable access hands the caller a register address and lets it do its own\u000aMMIO, so reading one entry looks like this:\u000a\u000a struct table_reg *q = rtl_table_get(RTL8380_TBL_L2, 0);\u000a\u000a rtl_table_read(q, idx);\u000a for (int i = 0; i < 3; i++)\u000a r[i] = sw_r32(rtl_table_data(q, i));\u000a\u000a rtl_table_release(q);\u000a\u000aThe driver has 89 of those sequences and computes a data register\u000aaddress 205 times. Move the register access into the table code, name\u000aeach table after itself rather than after the register and type value\u000athat select it, and let the caller pass a buffer:\u000a\u000a otto_table_read(RTL8380_TBL_L2_UC, idx, &r);\u000a\u000aThe names, the width of an entry and the number of rows are Realtek's\u000aown, taken from the table lists in the GPL SDK\u000a(src/hal/chipdef//rtk__table_list.c), with the register a\u000atable belongs to taken from the access group its _table_read()\u000aselects. Tables sharing a type value are one set of rows decoded in\u000adifferent layouts; each keeps its own name and its own width, because\u000aon five of the thirteen shared slots the width differs. The four\u000aRTL9300 host route tables are the one place where the SDK count is not\u000athe bound: they hold six entries in every eight addresses, and l3.c\u000atranslates before it calls, so the map carries the 8192 of the address\u000aspace rather than the 6144 entries.\u000a\u000aA caller names a table by its id and gets back a handle, an int\u000aindexing the driver's own data. Ids start at 1000 and handles at 0, so\u000apassing one where the other belongs is refused rather than quietly\u000aaccepted.\u000a\u000a #define otto_table_read(id, idx, p) \\\u000a otto_table_read_bytes((id), (idx), (p), otto_table_size(p))\u000a\u000amoves a whole entry and covers every caller. otto_table_size() takes\u000athe length from the caller's own object, so a buffer narrower than the\u000atable can no longer be overrun, where before the transfer length was a\u000aliteral repeated at each call site and tied to nothing. A bare array is\u000arefused at compile time, and TBL_MAP() asserts every width against the\u000awindow of the register it sits on, so a table wider than its window\u000acannot be described at all.\u000a\u000aAn index outside the table is refused. The mask the command register\u000aapplies to it cannot stand in for that check: the field is wider than\u000athe table on 66 of the 104 and exactly as wide on the other 38, and six\u000atables do not have a power-of-two row count at all. The refusal carries\u000aa WARN_ONCE; the splat is one-shot, the refusal is not. No index a\u000ashipping image can produce reaches the row count of the table it names:\u000athe paths that could are in the RTL930x L3 offload, which no subtarget\u000aconfig enables, and they predate this series.\u000a\u000aBoth read entry points clear their output first, since no caller looks\u000aat a return value. __otto_table_read_bytes() clears the caller's\u000abuffer, and __otto_table_fetch(), whose output is the data window\u000aitself, clears that window before the command. A refused read then\u000ahands back zeroes rather than the caller's stack or the row a previous\u000atransaction left behind. A timeout still copies the window, so that a\u000aread-modify-write commits the row as the hardware left it.\u000a\u000aThe window clear is new register traffic on RTL931x, its only user: 53\u000awrites per standard counter fetch and 28 per private one, so 2101 per\u000aport for the 42 counters the poll refreshes every three seconds, and\u000a1003 for a full ethtool -S. The SDK writes those registers only ahead\u000aof a write command, never before a read, so this has no vendor\u000aprecedent and is not verified on silicon. The word accessor now clamps\u000aboth ends of the window, so the one counter whose computed offset comes\u000aout negative reads the first word of the entry where it used to read a\u000aregister outside it.\u000a\u000aTwo further changes are deliberate. The PIE rule writers invalidated a\u000arule by committing whatever a previous transaction had left in the data\u000aregisters, and now commit the zeroed entry the function already\u000aprepares; on RTL838x that same exit is taken when the actions do not\u000afit, where the entry is half built. rtl930x_packet_cntr_clear() moves\u000athe whole row through a buffer rather than poking one data register,\u000akeeping the read-before-clear main already has.\u000a\u000aOf the four families only RTL930x is available here, and the series has\u000anot been run on it either.\u000a\u000aCompile-tested on realtek/rtl839x and realtek/rtl930x.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25062\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 20:18:58 +0200", "id" : "9f62ca8ff14d701928b425b53d0093de80eb0df6", "msg" : "realtek: table: read and write whole table entries", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/table.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" ], "commitId" : "0768ca4c67883b6808c66c601e33d2aa0af151ff", "timestamp" : 1788895713000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl931x: fix the FlexibleOctetsCRCSet1 offsets\u000a\u000artldsa_931x_stat_port_table_read() takes a counter out of an entry as\u000afield_offset - mib_offset, where field_offset is the last word of the\u000atable. That is the SDK's own arithmetic: table_field_get() computes\u000adatareg_num - 1 - (lsp >> 5) in hal/mac/mem.c, so mib_offset has to be\u000athe field's lsp divided by 32.\u000a\u000aTwo entries do not satisfy it. tx_PktsFlexibleOctetsCRCSet1 carries 28\u000afor a table 28 words wide, which lands one word below the data window,\u000aon the table command register; since 9f62ca8ff1 the word accessor\u000aclamps that to the first word. rx_PktsFlexibleOctetsCRCSet1 carries 27,\u000awhich is the first word, so it reports rx_UndersizeDropPkts: two\u000aethtool names, one counter.\u000a\u000aThe GPL SDK puts both fields in the private counter table at lsp 640\u000aand 608 (src/hal/chipdef/mango/rtk_mango_tableField_list.c), so the\u000aoffsets are 20 and 19. With those, the private entries are the\u000adescending run their neighbours already follow, and every offset in the\u000alist equals the lsp/32 of a distinct field. No offset in the driver\u000acomes out negative any more, so the note about that goes with them.\u000a\u000aSource analysis only, against the GPL SDK. No RTL9310 was available to\u000aread the two counters before and after.\u000a\u000aCompile-tested on realtek/rtl931x.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25083\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 21:28:33 +0200", "id" : "0768ca4c67883b6808c66c601e33d2aa0af151ff", "msg" : "realtek: dsa: rtl931x: fix the FlexibleOctetsCRCSet1 offsets", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" ], "commitId" : "769116266bb9d67b5d0cd30c7eb018e796d6aa7e", "timestamp" : 1788895713000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl931x: fix the single collisions offset\u000a\u000a.single_collisions carries offset 35, which is word 17 of the standard\u000acounter table, DOT1DTPPORTINDISCARDS. The counter the field names,\u000aDOT3STATSSINGLECOLLISIONFRAMES, is at lsp 1088 in the GPL SDK field\u000alist (src/hal/chipdef/mango/rtk_mango_tableField_list.c), so the offset\u000ais 34 and the word 18.\u000a\u000aA port therefore reports one counter under two names: as\u000adot1dTpPortInDiscards in ethtool -S, which reads offset 35 from the\u000asame table, and as SingleCollisionFrames in the eth-mac group, which\u000atakes .single_collisions from the counter poll.\u000a\u000aThe offset stays inside the table, so it produced a plausible number\u000arather than a read outside the window, and nothing in the driver\u000areports either case.\u000a\u000aSource analysis only, against the GPL SDK. No RTL9310 was available to\u000aread the counter before and after.\u000a\u000aCompile-tested on realtek/rtl931x.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25083\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-08 21:28:33 +0200", "id" : "769116266bb9d67b5d0cd30c7eb018e796d6aa7e", "msg" : "realtek: dsa: rtl931x: fix the single collisions offset", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl931x.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "8ecfbbe00290c1fdc0fea15a50972097ecff92af", "timestamp" : 1788941999000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: pass priv to the packet counter ops, use dev_dbg\u000a\u000aThe per-SoC packet_cntr_read() / packet_cntr_clear() ops only had the\u000araw counter index to work with, so their tracing went through\u000apr_debug(\"In %s ...\", __func__). Give both ops a struct\u000artl838x_switch_priv *priv argument - every call site already has one -\u000adrop the __func__ noise and describe what the call does with dev_dbg().\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25076\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 10:19:59 +0200", "id" : "8ecfbbe00290c1fdc0fea15a50972097ecff92af", "msg" : "realtek: dsa: rtl83xx: pass priv to the packet counter ops, use dev_dbg", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl930x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl838x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl839x.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/l3.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac", "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dtso", "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dtso", "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts" ], "commitId" : "235fe894cf1ee67b2fd713fe071afd5beaca37e5", "timestamp" : 1788948213000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: filogic: cmcc rax3000m: use mac-address nvmem cells\u000a\u000aAdd two mac-base nvmem cells (macaddr_factory_4, macaddr_factory_a)\u000aand map them as per-band mac-address entries in the emmc and nand\u000aDTS overlays.\u000a\u000aSince the per-band entries are added as addressed band@0/band@1\u000achild nodes, declare #address-cells = <1> and #size-cells = <0> on\u000athe shared &wifi node in mt7981b-cmcc-rax3000m.dts.\u000a\u000aRemove the cmcc,rax3000m special case from the ieee80211 hotplug\u000ascript, which previously read eth0. MAC address assignment is now\u000ahandled via DT/nvmem instead.\u000a\u000aVerified the resulting MAC addresses are unchanged.\u000a\u000aSigned-off-by: Andrii Kuiukoff \u000aLink: https://github.com/openwrt/openwrt/pull/24575\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:03:33 +0200", "id" : "235fe894cf1ee67b2fd713fe071afd5beaca37e5", "msg" : "mediatek: filogic: cmcc rax3000m: use mac-address nvmem cells", "paths" : [ { "editType" : "edit", "file" : "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-nand.dtso" }, { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac" }, { "editType" : "edit", "file" : "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts" }, { "editType" : "edit", "file" : "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-emmc.dtso" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch", "package/boot/uboot-mediatek/Makefile" ], "commitId" : "6350d57c00283693b8befd532512a6fc2f595f5f", "timestamp" : 1788948214000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "uboot-mediatek: cmcc rax3000m: add UBI variant\u000a\u000aAdd the CMCC RAX3000M(e) UBI-enabled U-Boot target for both DDR3 and DDR4 builds.\u000aRefactor the CMCC RAX3000M(e) device trees.\u000aThe board-specific DTS variants for eMMC, NAND, and UBI now\u000ainherit the common setup while overriding the required\u000aflash configuration and partitions.\u000aThis keeps the common MT7981 wiring centralized and\u000amakes each RAX3000M variant explicit and maintainable.\u000a\u000aSigned-off-by: Andrii Kuiukoff \u000aLink: https://github.com/openwrt/openwrt/pull/24575\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:03:34 +0200", "id" : "6350d57c00283693b8befd532512a6fc2f595f5f", "msg" : "uboot-mediatek: cmcc rax3000m: add UBI variant", "paths" : [ { "editType" : "edit", "file" : "package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch" }, { "editType" : "edit", "file" : "package/boot/uboot-mediatek/Makefile" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/image/filogic.mk", "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-ubi.dtso" ], "commitId" : "a55d09d2917a55ab2eeb2dd5bb0866bb4cd9b524", "timestamp" : 1788948214000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: filogic: cmcc rax3000m: add all-in-UBI layout\u000a\u000aThis commit introduces OpenWrt U-Boot all-in-UBI layout support\u000afor the CMCC RAX3000M / RAX3000Me, enabling:\u000a- Prolonged device lifetime by allocating most of the flash\u000a to UBI (which takes care of wear-leveling)\u000a- Maximum available storage space for OpenWrt\u000a\u000aOpenWrt U-Boot UBI flash instructions\u000a-------------------------------------\u000aA device running stock firmware should be upgraded to the\u000alatest OpenWrt firmware\u000a(https://firmware-selector.openwrt.org/?target=mediatek%2Ffilogic&id=cmcc_rax3000m).\u000a\u000aBack up critical data\u000a---------------------\u000aLuCI Web-UI:\u000a\"System\" -> \"Backup / Flash Firmware\" -> \"Save mtdblock contents\"\u000aSave mtdblock:\u000a factory\u000a\u000aMake sure the file were successfully downloaded to your downloads directory.\u000a\u000aUsing the installer image\u000a-------------------------\u000aTo simplify the installation process, this method uses a fork\u000aof Daniel Golle's (@dangowrt) UBI Installer\u000ahttps://github.com/dangowrt/owrt-ubi-installer\u000a\u000a1. Ensure your router is running the latest OpenWrt firmware.\u000a Upgrade it if necessary.\u000a2. Obtain the installer image:\u000a Build the installer from source according to your device variant\u000a https://github.com/andros-ua/owrt-ubi-installer/tree/rax3000m-ddr3\u000a or\u000a https://github.com/andros-ua/owrt-ubi-installer/tree/rax3000m-ddr4\u000a or download a prebuilt image from the\u000a https://github.com/andros-ua/owrt-ubi-installer/releases\u000a3. Flash the openwrt*-initramfs-recovery-installer.itb\u000a image using sysupgrade.\u000a4. Wait for installation:\u000a the green status LED will blink rapidly,\u000a indicating that the all-in-UBI installer is running.\u000a Once the installation finishes,\u000a the status LED will turn solid amber for 5 seconds.\u000a5. After the device reboots, perform a final sysupgrade using the\u000a openwrt*-squashfs-sysupgrade.itb image.\u000a\u000aBL2 and FIP Recovery\u000a--------------------\u000aUse mtk_uartboot to recover corrupted BL2 or FIP via UART:\u000ahttps://github.com/981213/mtk_uartboot\u000a\u000aOpenWrt U-Boot layout\u000a----------------------------------------\u000a| dev: size erasesize name |\u000a| mtd4: 00100000 00020000 \"bl2\" |\u000a| mtd3: 00080000 00020000 \"u-boot-env\" |\u000a| mtd2: 00200000 00020000 \"factory\" |\u000a| mtd1: 00200000 00020000 \"fip\" |\u000a| mtd0: 07200000 00020000 \"ubi\" |\u000a----------------------------------------\u000a\u000aOpenWrt U-Boot UBI layout\u000a----------------------------------\u000a| dev: size erasesize name |\u000a| mtd1: 00100000 00020000 \"bl2\" |\u000a| mtd0: 07f00000 00020000 \"ubi\" |\u000a----------------------------------\u000a\u000aUpdate MAC table after inspecting the factory partition:\u000a----------------------------------------------------------------\u000a| Interface | MAC | Source | |\u000a|--------------|-------------------|---------------|-----------|\u000a| WAN (label) | 54:4d:d4:xx:xx:xx | factory, 0x24 | label |\u000a| LAN | 54:4d:d4:xx:xx:xx | factory, 0x2a | label + 3 |\u000a| WLAN 2.4 GHz | 54:4d:d4:xx:xx:xx | factory, 0x4 | label + 1 |\u000a| WLAN 5 GHz | 54:4d:d4:xx:xx:xx | factory, 0xa | label + 2 |\u000a----------------------------------------------------------------\u000a\u000aSigned-off-by: Andrii Kuiukoff \u000aLink: https://github.com/openwrt/openwrt/pull/24575\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:03:34 +0200", "id" : "a55d09d2917a55ab2eeb2dd5bb0866bb4cd9b524", "msg" : "mediatek: filogic: cmcc rax3000m: add all-in-UBI layout", "paths" : [ { "editType" : "add", "file" : "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m-ubi.dtso" }, { "editType" : "edit", "file" : "target/linux/mediatek/image/filogic.mk" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version", "target/linux/mediatek/image/filogic.mk", "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts", "target/linux/mediatek/filogic/base-files/etc/board.d/02_network" ], "commitId" : "05e95a3bb5cac1d2a3ec4eb55fc95070c72de033", "timestamp" : 1788948214000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: filogic: cmcc rax3000m: label WAN port\u000a\u000aThe device has a label on the WAN port; add a matching DT openwrt,netdev-name.\u000a\u000aAdd openwrt,netdev-name = \"wan\" to gmac1 (mac@1) in mt7981b-cmcc-rax3000m.dts\u000ato identify the WAN port. Move the cmcc,rax3000m entry to the\u000aappropriate case block in\u000atarget/linux/mediatek/filogic/base-files/etc/board.d/02_network\u000aso mediatek_setup_interfaces handles the device correctly.\u000a\u000aBump the compat version so sysupgrade shows the warning message.\u000a\u000aSigned-off-by: Andrii Kuiukoff \u000aLink: https://github.com/openwrt/openwrt/pull/24575\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:03:34 +0200", "id" : "05e95a3bb5cac1d2a3ec4eb55fc95070c72de033", "msg" : "mediatek: filogic: cmcc rax3000m: label WAN port", "paths" : [ { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/etc/board.d/05_compat-version" }, { "editType" : "edit", "file" : "target/linux/mediatek/image/filogic.mk" }, { "editType" : "edit", "file" : "target/linux/mediatek/dts/mt7981b-cmcc-rax3000m.dts" }, { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/etc/board.d/02_network" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/apm821xx/nand/target.mk", "target/linux/apm821xx/image/nand.mk" ], "commitId" : "7a1684be88ad476d690e156716394795be1764b8", "timestamp" : 1788948333000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "apm821xx: add ubifs support\u000a\u000aubifs support can be added to have a single R/W volume for the device.\u000a\u000aCurrently only the MX60 enables it as the others are missing runtime\u000ainformation to enable usage.\u000a\u000aSigned-off-by: Rosen Penev \u000aLink: https://github.com/openwrt/openwrt/pull/25000\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:05:33 +0200", "id" : "7a1684be88ad476d690e156716394795be1764b8", "msg" : "apm821xx: add ubifs support", "paths" : [ { "editType" : "edit", "file" : "target/linux/apm821xx/nand/target.mk" }, { "editType" : "edit", "file" : "target/linux/apm821xx/image/nand.mk" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/base-files/etc/init.d/hwmon_fancontrol", "target/linux/realtek/base-files/etc/uci-defaults/04_dlinkfan", "target/linux/realtek/base-files/sbin/fan_ctrl.sh", "target/linux/realtek/base-files/etc/uci-defaults/04_dlinkfan_migration" ], "commitId" : "d3290efad9a97f1b49dabc5244ca0b6164ef0be0", "timestamp" : 1788948682000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "realtek: use autonomous LM63 fan control on DGS-1210-28P/MP\u000a\u000aPreviously, fan control on D-Link DGS-1210-28P/MP switches was handled\u000aby a user-space script (`fan_ctrl.sh`) triggered via cron every 5\u000aminutes due to missing kernel sysfs writable attributes for PWM\u000afrequency and hysteresis.\u000a\u000aThe `fan_ctrl.sh` contained a string-truncation comparison logic bug\u000a(temp1_input was truncated while PSU_THRESH was not) that kept the fan\u000alocked at a static 156 PWM (61%) rate regardless of temperature.\u000a\u000aAlso, since hwmon0 (cpu_thermal) appeared, it changed the order of hwmon\u000adevices and broke fan_ctrl.sh PWM control, keeping it always stopped.\u000a\u000aWith commit 89ef8aaf3e (\"kernel: backport lm63 enhancements\"),\u000a`pwm1_freq` and `pwm1_auto_point_temp_hyst` are now writable, enabling\u000afull autonomous LUT hardware fan management on the LM63 chip.\u000a\u000aTransition to autonomous hardware fan control:\u000a- Configure LM63 Look-up Table (LUT) via `/etc/init.d/hwmon_fancontrol`\u000a using the OEM register settings:\u000a * PWM Frequency: ~7826 Hz (PFR divisor 23)\u000a * Point 1: > 0°C -> PWM 28/46, 155/255 (~60.8% duty cycle)\u000a * Point 2: > 51°C -> PWM 46/46, 255/255 (100% duty cycle)\u000a * Points 3-8: > 127°C -> PWM 255/255 (chip defaults for unused points)\u000a * Hysteresis: 3°C (3000 mC)\u000a- Add `04_dlinkfan_migration` migration script to purge `fan_ctrl.sh` from\u000a crontab during sysupgrade.\u000a\u000aThe LM63 PWM resolution depends on the PFR divisor setting (2 * PFR).\u000aWith PFR set to 23 (matching OEM ~7826 Hz), full scale is 46 (0x2e). The\u000asysfs interface maps 0-255 to 0-46, meaning the OEM defaults 28 (0x1c)\u000aand 46 (0x2e) translate to sysfs values 155 (~60.8% duty cycle) and 255\u000a(100% duty cycle). Those values match the old fan_ctrl.sh temperature range\u000aand duty cycle.\u000a\u000aFixes: ab3f92e86481 (\"realtek: add fan controller support to D-Link DGS-1210-28MP\")\u000aSigned-off-by: Luiz Angelo Daros de Luca \u000aLink: https://github.com/openwrt/openwrt/pull/24869\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 12:11:22 +0200", "id" : "d3290efad9a97f1b49dabc5244ca0b6164ef0be0", "msg" : "realtek: use autonomous LM63 fan control on DGS-1210-28P/MP", "paths" : [ { "editType" : "add", "file" : "target/linux/realtek/base-files/etc/uci-defaults/04_dlinkfan_migration" }, { "editType" : "delete", "file" : "target/linux/realtek/base-files/etc/uci-defaults/04_dlinkfan" }, { "editType" : "edit", "file" : "target/linux/realtek/base-files/etc/init.d/hwmon_fancontrol" }, { "editType" : "delete", "file" : "target/linux/realtek/base-files/sbin/fan_ctrl.sh" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh", "package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic" ], "commitId" : "dcb5ede455e89bb682453133fc32a709e09343ec", "timestamp" : 1788954034000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: fix U-Boot env geometry for JioRouter AX6000 JIDU6101\u000a\u000aCorrect the U-Boot env geometry from \"0x80000\" \"1\" to \"0x1f000\" \"5\".\u000aThe correct LEB size for 128k PEB / 2k page is 0x1f000, and the 0x80000 volume spans 5 LEBs.\u000a\u000aThis also hardens jiorouter_initial_setup by adding proper error handling\u000aand dynamic UBI device/volume lookups, and generates /etc/fw_env.config to be consistent.\u000a\u000aSigned-off-by: Sheikh Faisal \u000aLink: https://github.com/openwrt/openwrt/pull/23510\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 13:40:34 +0200", "id" : "dcb5ede455e89bb682453133fc32a709e09343ec", "msg" : "mediatek: fix U-Boot env geometry for JioRouter AX6000 JIDU6101", "paths" : [ { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh" }, { "editType" : "edit", "file" : "package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/image/filogic.mk" ], "commitId" : "42eab6a9d30485e84f9a487172b907e75322ac32", "timestamp" : 1788954034000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: filogic: drop kmod-mt7916-firmware from JIDU6101\u000a\u000aThis device uses MT7976 radios and does not use the MT7916 blob.\u000aDrop the unnecessary firmware package.\u000a\u000aSigned-off-by: Sheikh Faisal \u000aLink: https://github.com/openwrt/openwrt/pull/23510\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 13:40:34 +0200", "id" : "42eab6a9d30485e84f9a487172b907e75322ac32", "msg" : "mediatek: filogic: drop kmod-mt7916-firmware from JIDU6101", "paths" : [ { "editType" : "edit", "file" : "target/linux/mediatek/image/filogic.mk" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac", "package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic", "target/linux/mediatek/dts/mt7986a-jiorouter-ax6000-jidu6j01.dts", "target/linux/mediatek/image/filogic.mk", "target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh", "target/linux/mediatek/filogic/base-files/etc/board.d/02_network" ], "commitId" : "552e617bd0ae18fce68fa1b9add4c4cc50da7d87", "timestamp" : 1788954034000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, "authorEmail" : "jonas@jonasjelonek.de", "comment" : "mediatek: add support for JioRouter AX6000 JIDU6J01\u000a\u000a| Component | Details |\u000a|------------------|------------------------------------------------|\u000a| **SoC** | MediaTek MT7986A (4× ARM Cortex-A53 @ 2.0 GHz) |\u000a| **RAM** | 512 MB |\u000a| **Flash** | 256 MB NAND |\u000a| **Ethernet** | 5× 10/100/1000 Mbps (1 WAN + 4 LAN) |\u000a| **WLAN 2.4 GHz** | MediaTek MT7976GN — 802.11b/g/n/ax, 4×4 MIMO |\u000a| **WLAN 5 GHz** | MediaTek MT7976AN — 802.11n/ac/ax, 4×4 MIMO |\u000a| **LEDs** | 1× RGB LED (GPIO-controlled) |\u000a| **Button** | 1× Reset |\u000a| **USB** | Yes |\u000a\u000a**MAC Addresses:**\u000a\u000a| Interface | Source |\u000a|------------|-------------------------------------------------|\u000a| WAN/Label | MFG MTD partition (variant-specific fallback) |\u000a| LAN | WAN + 1 |\u000a| 2.4 GHz | WAN + 2 |\u000a| 5 GHz | WAN + 3 |\u000a\u000aSupported variants and MAC source:\u000a- JIDU6J01,JIDU6201: binary at offset 0x00\u000a- JIDU6401: binary at offset 0x20\u000a- JIDU6601: ASCII text at offset 0x1d0\u000a- JIDU6701: ASCII mac= key\u000a\u000a---\u000a\u000a**1. Extracting U-Boot Credentials**\u000aThe U-Boot username and password are stored in the `MFG` partition. To retrieve them:\u000a- With root access on stock OS: Read directly from the MFG partition.\u000a- Without root access: Dump the NAND flash first, then extract the credentials from the dump.\u000a\u000a**2. Prepare TFTP server**\u000a- Set a static IP on the ethernet interface of your computer\u000a (e.g. default: ip `192.168.1.2`, gateway `192.168.1.1`).\u000a- Download the initramfs image and host it with the TFTP server.\u000a\u000a**3. Interrupt boot**\u000a\u000aAttach UART and power on the router. When the boot menu appears, select **Failsafe Mode**,\u000athen press `Ctrl-C` to interrupt and enter the credentials extracted from `MFG` partition.\u000a\u000a**4. Load and run initramfs image**\u000a```sh\u000asetenv ipaddr 192.168.1.1\u000asetenv serverip 192.168.1.2\u000atftpboot 0x46000000 openwrt-mediatek-filogic-jiorouter_ax6000-jidu6j01-initramfs-kernel.bin\u000afdt addr $(fdtcontroladdr)\u000afdt rm /signature\u000abootm\u000a```\u000a\u000a**5. Flash sysupgrade image**\u000a\u000aPlace the sysupgrade image in `/tmp`, then run:\u000a```sh\u000asysupgrade /tmp/openwrt-mediatek-filogic-jiorouter_ax6000-jidu6j01-squashfs-sysupgrade.bin\u000a```\u000aAlternatively, use the sysupgrade option in LuCI.\u000a\u000aSigned-off-by: Sheikh Faisal \u000aLink: https://github.com/openwrt/openwrt/pull/23510\u000aSigned-off-by: Jonas Jelonek \u000a", "date" : "2026-09-09 13:40:34 +0200", "id" : "552e617bd0ae18fce68fa1b9add4c4cc50da7d87", "msg" : "mediatek: add support for JioRouter AX6000 JIDU6J01", "paths" : [ { "editType" : "edit", "file" : "package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic" }, { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh" }, { "editType" : "edit", "file" : "target/linux/mediatek/image/filogic.mk" }, { "editType" : "add", "file" : "target/linux/mediatek/dts/mt7986a-jiorouter-ax6000-jidu6j01.dts" }, { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/etc/board.d/02_network" }, { "editType" : "edit", "file" : "target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "package/utils/adb/patches/010-mbedtls.patch", "package/utils/adb/Makefile" ], "commitId" : "5f62b79d1cf7ee0c903aa98995828a49c26dd1d4", "timestamp" : 1788968010000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "adb: fix RSA authentication with mbedTLS\u000a\u000aADB authentication signs the 20-byte challenge directly as a SHA-1\u000adigest. The mbedTLS port hashes the challenge before signing it,\u000acausing adbd to reject every signature and request user approval\u000aafter each server restart.\u000a\u000aPass the challenge directly to mbedtls_pk_sign(), matching the former\u000aRSA_sign() behavior.\u000a\u000aSigned-off-by: Vladimir Zadirei \u000aLink: https://github.com/openwrt/openwrt/pull/24946\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 17:33:30 +0200", "id" : "5f62b79d1cf7ee0c903aa98995828a49c26dd1d4", "msg" : "adb: fix RSA authentication with mbedTLS", "paths" : [ { "editType" : "edit", "file" : "package/utils/adb/patches/010-mbedtls.patch" }, { "editType" : "edit", "file" : "package/utils/adb/Makefile" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c" ], "commitId" : "e4e60164ba1d0544b84c0c79c08dcca8dfc8c05b", "timestamp" : 1788973759000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: fix mirror teardown on RTL839x/931x\u000a\u000artldsa_port_mirror_del() clears the port's bit with the family accessor\u000apriv->r->mask_port_reg_be(), then decides whether the mirror group has\u000abecome empty with a plain sw_r32(). On RTL839x and RTL931x the source\u000aand destination port matrices are 64 bit wide: their registers are\u000aspaced group * 8, and mask_port_reg_be() writes bits 63:32 at reg and\u000abits 31:0 at reg + 4. A single sw_r32() therefore reads only the word\u000aholding ports 32 and above, so the bits of ports 0 to 31 are invisible\u000ato the test.\u000a\u000aMirrors that share a monitor port share a group. Remove one of them\u000awhile every remaining source port is below 32, and the test reads zero\u000aand takes the teardown branch: MIR_CTRL is overwritten while the\u000amatrices still carry the surviving ports. Mirroring stops for a rule\u000athat tc still lists, and the group is marked free although it is not.\u000a\u000aRead the matrices with priv->r->get_port_reg_be(), which is what the\u000atwin rtldsa_port_mirror_add() already uses on the same matrix.\u000a\u000aThe register widths come from the Realtek GPL SDK register lists:\u000asrc/hal/chipdef/cypress/rtk_cypress_reg_list.c gives MIR_SPM_CTRL at\u000a0x2510 with a bit offset of 64, rtk_mango_reg_list.c gives 0xAF10 with\u000a64 as well, while rtk_longan_reg_list.c gives 0xA2B0 with 32.\u000a\u000aRTL838x and RTL930x are unaffected: .get_port_reg_be is\u000artl838x_get_port_reg() there, whose body is return ((u64)sw_r32(reg)),\u000aso the new expression performs the same read, and their matrices are\u000asingle 32 bit registers anyway.\u000a\u000aCompile-tested on realtek/rtl839x, realtek/rtl931x and realtek/rtl930x.\u000aNot tested on hardware: no RTL839x or RTL931x board is available here.\u000aReported in https://github.com/openwrt/openwrt/issues/25087, which\u000acarries a test procedure for someone who has one.\u000a\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Gennaro Cimmino \u000aLink: https://github.com/openwrt/openwrt/pull/25088\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 19:09:19 +0200", "id" : "e4e60164ba1d0544b84c0c79c08dcca8dfc8c05b", "msg" : "realtek: dsa: fix mirror teardown on RTL839x/931x", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/patches-6.18/821-add-realtek-pcie-phy-driver.patch", "target/linux/realtek/files-6.18/drivers/phy/realtek/phy-rtk-pcie.c" ], "commitId" : "bb00e9f0974f483dfb4a88e6c50331b9aa783c78", "timestamp" : 1788977794000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: phy: add support for rtl9607c pcie phy\u000a\u000aAdd the support for PCIE PHY found in Realtek SoCs. For now, only RTL9607C\u000arevisions A and B are supported but other chips like RTL8198C could be added\u000aas well if they are similar enough.\u000a\u000aMost of the code was copied over from phy-rtk-usb3 driver as they both have\u000astriking similarities in phy calibration with some added changes that address\u000aflaws of phy-rtk-usb3. The other bits have come from pci driver from GPL source\u000athat seem most relevant to PHY side compared to PCIE controller side.\u000a\u000aThis PHY driver is gonna be used by the Realtek PCIE controller in the next\u000apatch of this series.\u000a\u000aCo-developed-by: Michael Zavertkin \u000aSigned-off-by: Michael Zavertkin \u000aSigned-off-by: Rustam Adilov \u000aLink: https://github.com/openwrt/openwrt/pull/24983\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:16:34 +0200", "id" : "bb00e9f0974f483dfb4a88e6c50331b9aa783c78", "msg" : "realtek: phy: add support for rtl9607c pcie phy", "paths" : [ { "editType" : "add", "file" : "target/linux/realtek/patches-6.18/821-add-realtek-pcie-phy-driver.patch" }, { "editType" : "add", "file" : "target/linux/realtek/files-6.18/drivers/phy/realtek/phy-rtk-pcie.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/spaces.h", "target/linux/realtek/files-6.18/drivers/pci/controller/pcie-realtek.c", "target/linux/realtek/patches-6.18/822-add-realtek-pcie-controller-driver.patch" ], "commitId" : "779c6d37691a3b8f5b1496b2b5c04f7e3821aeb7", "timestamp" : 1788977794000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: pci: add rtl9607c pcie controller support\u000a\u000aThis patch adds support for PCIE controller found on Realtek SoCs\u000alike RTL9607C/RTL8198D. At this moment, only RTL9607C/RTL8198D are\u000asupported but the RTL8198C could be added as they seem to be quite\u000asimilar.\u000a\u000aPCIE controller on RTL9607C / RTL8198D SoCs have 2 PCIE ports, one\u000afor 2.4G wifi chipset and the other for 5G wifi chipset.\u000a\u000aThe spaces.h header is also added with the size of 0x10000 for each\u000aPCIe port so that both IO resources could have space to be assigned.\u000a\u000aThe initial version of the pcie controller driver was written by\u000aNaseef, which later on was split into seperate PHY and controller\u000aparts and made more upstream friendly.\u000a\u000aCo-developed-by: Ahmed Naseef \u000aSigned-off-by: Ahmed Naseef \u000aCo-developed-by: Michael Zavertkin \u000aSigned-off-by: Michael Zavertkin \u000aSigned-off-by: Rustam Adilov \u000aLink: https://github.com/openwrt/openwrt/pull/24983\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:16:34 +0200", "id" : "779c6d37691a3b8f5b1496b2b5c04f7e3821aeb7", "msg" : "realtek: pci: add rtl9607c pcie controller support", "paths" : [ { "editType" : "add", "file" : "target/linux/realtek/files-6.18/arch/mips/include/asm/mach-rtl-otto/spaces.h" }, { "editType" : "add", "file" : "target/linux/realtek/files-6.18/drivers/pci/controller/pcie-realtek.c" }, { "editType" : "add", "file" : "target/linux/realtek/patches-6.18/822-add-realtek-pcie-controller-driver.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "85d9dbad33a0420c8404eb4f26c1b137e4425fcb", "timestamp" : 1788980265000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: give the tc flow hashtable a real lifecycle\u000a\u000aThe rhashtable that stores offloaded tc flows was initialised lazily from\u000aa \"first_time\" static in rtl83xx_setup_tc() and never torn down. Add\u000artldsa_tc_init() / rtldsa_tc_cleanup() helpers, track initialisation in\u000athe switch private data, set the table up in rtldsa_93xx_setup() and free\u000ait (RCU-safely) from rtl83xx_sw_remove() and the probe error path.\u000a\u000aThis changes two things for the existing (rtl930x only) user:\u000a\u000a - \"first_time\" was a function-scope static shared by every switch\u000a instance, so on a multi-switch system only the first one to take a\u000a TC_SETUP_BLOCK ever got a tc_ht. Each switch now gets its own at\u000a probe.\u000a - a table init failure is propagated out of probe instead of only\u000a being logged while setup continues.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25094\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:57:45 +0200", "id" : "85d9dbad33a0420c8404eb4f26c1b137e4425fcb", "msg" : "realtek: dsa: rtl83xx: give the tc flow hashtable a real lifecycle", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/common.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/dsa.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h", "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "0c4e7603be4d1a62ea5d9203342db0fc97e32447", "timestamp" : 1788980266000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: serialize the tc flower add/del/stats callbacks\u000a\u000aThe tc cls_flower add / del / stats callbacks reach per-switch state -\u000athe flow hashtable, the PIE rule IDs and the LOG counters - that has no\u000aserialization of its own. Every caller currently runs under rtnl\u000a(dsa_user_setup_tc_block() does not set unlocked_driver_cb, so\u000atcf_block_bind() bumps block->lockeddevcnt and tc_setup_cb_*() takes\u000artnl), so this is not a bug that can be hit today, but nothing in the\u000adriver documents or enforces that. It also leaves\u000artldsa_configure_flower() publishing a flow into tc_ht before\u000apie_rule_add() has assigned its rule ID, where an unlocked delete racing\u000athe add would call pie_rule_rm() with rule.id still 0 and tear down an\u000aunrelated PIE rule.\u000a\u000aAdd a per-switch tc_flow_lock mutex, set up and torn down alongside the\u000aflow hashtable, and hold it across the whole body of\u000artldsa_configure_flower(), rtldsa_delete_flower() and\u000artldsa_stats_flower(). This makes the serialization explicit and local\u000arather than an unstated reliance on the caller. tc_flow_lock is the\u000aoutermost tc lock - reg_mutex and pie_mutex are always taken under it,\u000anever the other way round.\u000a\u000aThe three callbacks are reworked here, so also rename them from the\u000artl83xx_ to the rtldsa_ prefix to match the surrounding tc flower code.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25094\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:57:46 +0200", "id" : "0c4e7603be4d1a62ea5d9203342db0fc97e32447", "msg" : "realtek: dsa: rtl83xx: serialize the tc flower add/del/stats callbacks", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" }, { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/rtl-otto.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "b7838d861f869631e41c8b8c7c6e22a43fdc75ff", "timestamp" : 1788980266000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: read the tc flow counter outside the RCU lock\u000a\u000artldsa_stats_flower() looked the flow up without rcu_read_lock() at all\u000aand then called packet_cntr_read(), which sleeps.\u000a\u000aDo the rhashtable lookup in a short RCU section and read the hardware\u000acounter with reg_mutex held once RCU is dropped; tc_flow_lock (held for\u000athe whole callback) keeps the flow alive across the read. Use u32 for the\u000apacket counters, return -ENOENT when the flow is gone, switch the debug\u000aprint to dev_dbg(), and report the real packet count instead of a\u000asynthetic byte estimate.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25094\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:57:46 +0200", "id" : "b7838d861f869631e41c8b8c7c6e22a43fdc75ff", "msg" : "realtek: dsa: rtl83xx: read the tc flow counter outside the RCU lock", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "1d398b5cc3c508280e6c1744c84962557c07e74c", "timestamp" : 1788980266000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: release a flow's LOG counter when it is destroyed\u000a\u000artldsa_configure_flower() allocates a LOG-table packet counter with\u000artldsa_packet_cntr_alloc(), but the flow teardown paths\u000a(rtldsa_tc_flow_free() and rtldsa_delete_flower()) never called\u000artldsa_packet_cntr_free(), so every removed offloaded flow leaked its\u000acounter slot until the bitmap filled up.\u000a\u000aAdd rtldsa_packet_cntr_release(): zero the hardware counter and hand the\u000aslot back, in that order, so a slot is never returned to the allocator\u000awhile the hardware entry still holds the previous flow's count. Call it\u000afrom both teardown paths and from the configure error unwind (which\u000aalready freed the slot but left the hardware counter dirty). The helper\u000ais a no-op while no counter is assigned (rule.packet_cntr starts at -1).\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25094\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:57:46 +0200", "id" : "1d398b5cc3c508280e6c1744c84962557c07e74c", "msg" : "realtek: dsa: rtl83xx: release a flow's LOG counter when it is destroyed", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" ], "commitId" : "a92bb742978d9531cd5b9ecbd68ad28505b18ef6", "timestamp" : 1788980266000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, "authorEmail" : "markus.stockhausen@gmx.de", "comment" : "realtek: dsa: rtl83xx: hold tc_flow_lock in rtldsa_tc_cleanup()\u000a\u000aThe add, delete and stats cls_flower callbacks all run under\u000atc_flow_lock, but rtldsa_tc_cleanup() walked and destroyed tc_ht\u000awithout it and then destroyed the mutex. A callback that raced teardown\u000acould therefore walk a flow that rtldsa_tc_flow_free() is freeing, or\u000acall pie_rule_rm() on a rule this path already removed.\u000a\u000aTake tc_flow_lock around rhashtable_free_and_destroy() and clear\u000atc_initialized under it, so any in-flight callback completes before the\u000atable is torn down. Drop the lock before rcu_barrier() / mutex_destroy().\u000a\u000aA callback that was already blocked on tc_flow_lock when teardown ran\u000awould still wake into a freed tc_ht, so the three callbacks re-check\u000atc_initialized right after they take the lock and return -ENODEV when\u000ait is clear.\u000a\u000aAssisted-by: Claude Code (Anthropic Claude Sonnet 5)\u000aSigned-off-by: Mark Abe \u000aLink: https://github.com/openwrt/openwrt/pull/25094\u000aSigned-off-by: Markus Stockhausen \u000a", "date" : "2026-09-09 20:57:46 +0200", "id" : "a92bb742978d9531cd5b9ecbd68ad28505b18ef6", "msg" : "realtek: dsa: rtl83xx: hold tc_flow_lock in rtldsa_tc_cleanup()", "paths" : [ { "editType" : "edit", "file" : "target/linux/realtek/files-6.18/drivers/net/dsa/rtl83xx/tc.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "51e2f22a91b98c3ff57fa931d7fb69cde485c073", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: make the bridge VLAN translation rules match\u000a\u000aAn ingress VLAN translation rule selects the frames it applies to with two\u000aframe-format fields, and both are match bitmaps: a zero matches no frame at\u000aall. ppe_xlt_rule_set() only ever wrote the C-tag side, so every rule the\u000abridge VLAN path installs has been inert since the driver was added - no\u000abridge VLAN has ever been classified into its own VSI in hardware. Readback\u000aon IPQ8074 with a VLAN-filtering bridge shows the S-tag format zero on the\u000arule.\u000a\u000aSetting it is half the fix. Live, the rule then applies its action, and the\u000aaction deletes the C-tag: the frame reaches the CPU untagged, the software\u000abridge reads it as the port's PVID rather than the VLAN it arrived on, and\u000ait never reaches that VLAN's upper device. So the rule classifies and\u000anothing more - the VSI carries the domain from there, and which ports\u000aegress the VLAN untagged is already EG_VSI_TAG's decision, programmed by\u000appe_eg_vsi_tag_port_set().\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44) with br-lan over lan1-3,\u000aVID 20 tagged on one port and a tagged client on it. One register write\u000aapart: with the tag edit the VLAN's upper device receives nothing, without\u000ait the client passes traffic over the VLAN.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "51e2f22a91b98c3ff57fa931d7fb69cde485c073", "msg" : "qualcommax: qca_ppe: make the bridge VLAN translation rules match", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "a8402a5218bee8b49250d1b5b0f0783bf84ee16c", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: keep a bridge VLAN across a filtering toggle\u000a\u000aA translation rule that is live has to stop classifying while its bridge\u000adoes not filter, and start again when it does. The driver opted into the\u000alegacy DSA behaviour instead, where a port under a bridge with\u000avlan_filtering=0 is offered no VLAN configuration at all; the bridge VLANs\u000athen reach the hardware neither while filtering is off nor when it comes\u000aback on, which net/dsa/user.c describes as broken and discouraged.\u000a\u000aTake the default, record the bridge VLANs either way, and mask the port out\u000aof the rules and the VSI member set while it does not filter. A port that\u000astarts filtering reprograms every VLAN entry naming it from the state the\u000adriver kept.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44) with br-lan over lan1-3\u000aand VID 20 tagged on one port. While filtering is off the VLAN's rule reads\u000aback valid with an empty port bitmap and its VSI with an empty member mask;\u000awith filtering on the same rule names the three ports and the CPU port.\u000aThree off-and-on cycles leave the translation, action and VSI tables\u000abyte-identical to the state before the first cycle, and the port forwards\u000aafter each one.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "a8402a5218bee8b49250d1b5b0f0783bf84ee16c", "msg" : "qualcommax: qca_ppe: keep a bridge VLAN across a filtering toggle", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "8826898af11eb883d0d44a64b33c0b98f5010fa6", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: release a port's old pvid rule when its pvid changes\u000a\u000aThe bridge announces a new pvid as an add of that vid alone, so the entry\u000aholding the port's untagged rule is never told it lost the port. It keeps\u000athe port in its pvid set, and two translation rules then claim the same\u000aport's untagged frames.\u000a\u000aDrop the port from the entry its previous pvid names before the new entry\u000atakes it.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "8826898af11eb883d0d44a64b33c0b98f5010fa6", "msg" : "qualcommax: qca_ppe: release a port's old pvid rule when its pvid changes", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "22eb4678992cd10b4173e166dec2dd69ef55fa1e", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: program a VLAN's translation action before its rule\u000a\u000aA VLAN's translation rule is made live before the action that names the VSI\u000ait classifies into. The action of a freshly allocated index is all zeroes,\u000aso between the two writes a tagged frame matching the new rule takes no VSI\u000acommand and is bridged in the port's own domain rather than the VLAN's. The\u000ateardown path already clears the rule before the action; the setup path now\u000amirrors it.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "22eb4678992cd10b4173e166dec2dd69ef55fa1e", "msg" : "qualcommax: qca_ppe: program a VLAN's translation action before its rule", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "1b03fac5ccab921b9b9092c3fc0c54bfb9182635", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: name the translation-miss command for what it does\u000a\u000aPPE_XLT_MISS_FWD_DROP is the value PPE_VLAN_XLT_MISS_FWD takes on a port\u000athat filters, and the name says the hardware drops a frame whose VLAN no\u000atranslation rule matches. It does not: with filtering enabled on lan1-lan3\u000aand no rule matching their VLAN, an ssh session over lan1 and a ping across\u000alan3 both survive, so those frames are not discarded.\u000a\u000aThree is redirect-to-CPU in the forwarding-command encoding this hardware\u000auses, which the kernel's own ppe driver spells out:\u000a\u000a\u0009drivers/net/ethernet/qualcomm/ppe/ppe_config.h:\u000a\u0009\u0009PPE_ACTION_FORWARD = 0,\u000a\u0009\u0009PPE_ACTION_DROP = 1,\u000a\u0009\u0009PPE_ACTION_COPY_TO_CPU = 2,\u000a\u0009\u0009PPE_ACTION_REDIRECT_TO_CPU = 3,\u000a\u000aand which this driver already carries in PPE_APP_CTRL_REDIRECT_CPU. Name\u000athis one to match.\u000a\u000aThe value and the behaviour are unchanged; only the name stops claiming the\u000aopposite of what the port does.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "1b03fac5ccab921b9b9092c3fc0c54bfb9182635", "msg" : "qualcommax: qca_ppe: name the translation-miss command for what it does", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" ], "commitId" : "585137af02dc210e6088653c002ac6e97c437a27", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: key the FDB and MDB on the VSI, not the vid\u000a\u000aThe PPE keys an L2 entry on the VSI the frame carries, not on the vid Linux\u000apassed.\u000a\u000appe_fdb_encode() put DSA's vid into the entry's VSI field, and so did the\u000amulticast encoder and the lookup key. A VLAN-unaware bridge passes vid 0,\u000aso every entry the driver wrote landed in VSI 0 - the standalone domain\u000areserved at setup - while the bridge forwards on a VSI allocated from 1 up.\u000aThe entries could never match. Hardware learning hides most of it: the PPE\u000alearns any address that transmits on a physical port into the frame's own\u000aVSI, so wired unicast switches correctly and nothing looks wrong. What is\u000aleft is exactly the set the hardware cannot learn, which is the only set\u000aDSA offloads - addresses behind the CPU port. On this board that is every\u000aWi-Fi station, installed by assisted_learning_on_cpu_port, plus the\u000arouter's own MACs. Each sat in VSI 0 and was never hit, so wired-to-Wi-Fi\u000aunicast stayed unknown and flooded the bridge. Multicast has no learning\u000afallback at all, so the MDB offload was a silent no-op.\u000a\u000aResolve the VSI where the bridge is known, at the DSA op, and pass a VSI\u000adown. A vid naming one of the driver's bridge VLANs gives that VLAN's VSI;\u000aany other vid, including the 0 a VLAN-unaware bridge passes, gives the\u000abridge's own VSI, which is the domain those frames are forwarded in. An\u000aentry that names no bridge resolves to nothing and is refused rather than\u000awritten into VSI 0. The dump had the same confusion in reverse, reporting\u000athe VSI as a vid, which printed a phantom \"vlan 1\" against every\u000ahardware-learned entry. It takes the inverse mapping here, because it is\u000athe same defect on the way out. Renaming the helpers' parameter is what\u000astops it coming back.\u000a\u000aThe lookup walks the bridge and VLAN state that the switchdev ops mutate,\u000aand DSA runs the FDB and MDB ops from an ordered workqueue that holds no\u000artnl, so both sides take a mutex. An MDB update reads an entry's port map\u000aand writes it back, which the same mutex makes atomic.\u000a\u000aTested on an AX3600 (IPQ8074, 6.18) with a VLAN-unaware br-lan over lan1-3\u000aand two APs. A full walk of the 2048 FDB entries showed both halves of the\u000adefect at once: 00:00:5e:00:53:01 at VSI 1 from the bridge's own vid 1\u000aentry and again at VSI 0 from the vid 0 one, with station 00:00:5e:00:53:02\u000atowards the CPU port at VSI 0. After the change no entry is left in VSI 0,\u000athe duplicate pair is one entry, and every station address is at VSI 1.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "585137af02dc210e6088653c002ac6e97c437a27", "msg" : "qualcommax: qca_ppe: key the FDB and MDB on the VSI, not the vid", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_vlan.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "c9278473d06ab8543b6d502dd8eb9774fb8fd183", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: let the FDB dump say it ran out of room\u000a\u000aqca_ppe_port_fdb_dump() walks all 2048 entries and hands each match to the\u000acallback, but it treats a failing callback as a reason to stop and then\u000areturns success. The failure that matters is -EMSGSIZE, which is how the\u000acallback says the netlink skb is full and the dump should resume from here.\u000aSwallowing it tells rtnl_fdb_dump() the port finished, so it discards the\u000acursor and moves to the next port, and `bridge fdb show` silently reports\u000afewer entries than the switch holds. A port busy enough to fill an skb is\u000aexactly the one whose table someone wants to read.\u000a\u000aReturn what the callback returned. The mutex is released by its guard\u000aeither way.\u000a\u000aThis is not a defect of the offload work in this series - the dump predates\u000ait - so it stands on its own and applies without the rest.\u000a\u000aNot reproduced here: filling a netlink skb needs far more entries than this\u000abench puts in the table, so what is shown is the contract, from\u000artnl_fdb_dump()'s handling of the return value.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "c9278473d06ab8543b6d502dd8eb9774fb8fd183", "msg" : "qualcommax: qca_ppe: let the FDB dump say it ran out of room", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "6831f7b9ef5b55b2932e7d320988097b2ccdd054", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: answer an FDB lookup only with a port map\u000a\u000appe_fdb_lookup() reports any valid entry as a port map, and its caller is\u000athe multicast path. A unicast entry carries a port number in the same\u000afield, so a group whose slot holds one is programmed with a member set it\u000awas never given - a multicast stream then egresses a port that never\u000ajoined. The sibling reader, ppe_fdb_read_entry(), already discriminates on\u000athe destination type.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "6831f7b9ef5b55b2932e7d320988097b2ccdd054", "msg" : "qualcommax: qca_ppe: answer an FDB lookup only with a port map", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "0f9baab7f64ee23bc5688b67dba3fd0d28aa2350", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: finish an FDB operation before reading its result\u000a\u000aThe FDB operation registers report the id of the command they last\u000afinished, and the driver waited on ids it had not issued. Four of the five\u000aoperations issued no id at all and waited for id zero, which is what the\u000aresult register reads back when it has posted nothing; the fifth, the entry\u000aread, issued an id taken from the entry index modulo fifteen, so every\u000afifteenth index waited for zero too. The wait therefore returned on the\u000afirst read, before the engine had run, and the result data registers were\u000aread while they still held whatever the previous operation left.\u000a\u000aA multicast group added this way could not be found again: the lookup its\u000adelete makes read all-zero data, reported the entry as absent, and the\u000aswitchdev core logged a failed delete while the hardware entry stayed\u000aprogrammed - a group kept receiving on a port after its last member left.\u000a\u000aEach operation now takes an id of its own, from one upward so that a\u000aregister which has posted nothing never answers for it, and each of the two\u000aresult registers counts on its own so an id is never the one its register\u000aalready holds. The result data is read once the register reports that id.\u000a\u000aMeasured on an ipq807x AX3600: a group added on two switch ports is\u000areported offloaded on both, each member deletes with no error and no\u000aswitchdev complaint, and a bridge FDB dump reads back the addresses learnt\u000aon the three user ports.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "0f9baab7f64ee23bc5688b67dba3fd0d28aa2350", "msg" : "qualcommax: qca_ppe: finish an FDB operation before reading its result", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "426681cfa40f8f2779d172dbb5b12f4899d2e2a3", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: latch the port VSI binding\u000a\u000aThis PPE takes the write to a table entry's last word as the commit, so an\u000aentry edited a word at a time is staged and never taken.\u000a\u000appe_port_vsi_set() rewrote only word 1 of L3_VP_PORT_TBL, so a runtime\u000abridge join never bound the port to its VSI in hardware and the entry kept\u000awhatever the previous binding left in it. Read-modify-write the whole\u000aentry, ascending.\u000a\u000appe_vsi_init() was this same dance done once at probe - its comment even\u000anames the rule - and the DSA setup path re-binds every port through the\u000afixed setter before traffic flows, so it goes.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): taking a user port out\u000aof the bridge and putting it back leaves L3_VP_PORT_TBL word 1 reading\u000a0x600 and 0x000 in turn, over two cycles - the valid bit and VSI 1, whose\u000amember mask names the CPU port and the three bridged user ports.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "426681cfa40f8f2779d172dbb5b12f4899d2e2a3", "msg" : "qualcommax: qca_ppe: latch the port VSI binding", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "cf23d39714907ceab452c55a416009263ead6106", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: commit the port MTU write instead of staging it\u000a\u000aThe per-port size check lives in MRU_MTU_CTRL_TBL, an entry that latches on\u000athe write to its second word. Setup gets there by accident: it writes the\u000asizes into word 0 and the counter enables reach word 1 later in probe, so\u000athe entry commits. port_change_mtu edited word 0 and stopped, which leaves\u000athe write staged, so every mtu the kernel handed down after probe was lost\u000aand the port kept the size probe had given it.\u000a\u000aBoth callers now go through one helper that reads word 1, writes the sizes\u000aand writes word 1 back unchanged; it carries the counter enables and the\u000asource profile, which this path knows nothing about.\u000a\u000aBeside each size field sits a two-bit command deciding what happens to a\u000aframe that fails the check, and the driver left all three alone, so the\u000asizes were compared against and then ignored. Set them the way mainline's\u000appe driver sets the same fields: a frame over the receive size goes to the\u000aCPU, which is where an oversized routed packet has to reach for the icmp\u000athat tells the sender to send less, and a frame over the transmit size is\u000adropped rather than sent back to a CPU that would only offer it to the same\u000aport again.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): setting a user port's\u000amtu to 1400 makes its entry read back 0x458ec58e - both sizes at 1422, the\u000areceive command redirect-to-CPU and the transmit command drop - and\u000a0x45f2c5f2 again at 1500, over three cycles, with word 1 holding the\u000acounter enables throughout and only the port whose mtu changed moving.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "cf23d39714907ceab452c55a416009263ead6106", "msg" : "qualcommax: qca_ppe: commit the port MTU write instead of staging it", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_scheduler.c" ], "commitId" : "2c4a0328af06a6ffa557dcb1a9fe9fde1f071744", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: set the QoS precedence per generation\u000a\u000aWhich classifier decides a packet's internal priority is a per-port field.\u000appe_qos_init() wrote it at PPE_PRX_BASE + 0x3000 + port * 0x10 + 4, in the\u000apacket-receive block. That offset, stride and word are the second word of a\u000aport's MRU/MTU entry at the stride ppe_data gives IPQ6018; the base is not\u000athe one PPE_MRU_MTU_CTRL() uses. IPQ8074's entry is eight bytes, so neither\u000athe address nor the field positions apply to it.\u000a\u000aSelect both from the SoC through one lookup that names the register and\u000aevery field: IPQ8074 gets PPE_PORT_QOS_CTRL, and IPQ6018 keeps the\u000apositions the driver already carried, on the MRU/MTU entry they address.\u000aAnything else that reaches these fields goes through the same lookup rather\u000athan open-code one generation's layout. The order asked for is unchanged -\u000aflow above preheader, then ACL, DSCP and PCP - and nothing gives the flow\u000asource an opinion, so the ranking below it decides.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): PPE_PORT_QOS_CTRL reads\u000aback 0x00014608 on every port, and forwarding and dmesg are unchanged. The\u000aIPQ6018 arm is not runtime tested - there is no IPQ6018 on the bench.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "2c4a0328af06a6ffa557dcb1a9fe9fde1f071744", "msg" : "qualcommax: qca_ppe: set the QoS precedence per generation", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_scheduler.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" ], "commitId" : "8990769d1f17367947b34abb3d650fd4ec1ada73", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: fix the multicast queue resume offset field\u000a\u000aA multicast queue's green resume offset is an 11-bit field at bit 71 of the\u000aentry, which is bits 17:7 of its third word, not 17:11. Written four bits\u000atoo high, the 36 the driver asks for reaches the hardware as 576 - a resume\u000athreshold below zero on a queue whose ceiling is 400, so a multicast queue\u000athat once filled has to drain much further than intended before it accepts\u000aagain.\u000a\u000aReadback on IPQ8074 confirms it: the word reads 0x00012000 on every\u000amulticast queue. Upstream's own driver for the later part has the span\u000aright (PPE_AC_MULTICAST_QUEUE_CFG_W2_RESUME, GENMASK(17, 7)).\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): the word reads\u000a0x00001200, multicast forwarding and an IPTV stream are undisturbed, and\u000admesg is clean.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "8990769d1f17367947b34abb3d650fd4ec1ada73", "msg" : "qualcommax: qca_ppe: fix the multicast queue resume offset field", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "00e31226cd78828080aea53addb208fc7e87f747", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: enable TX pause on an XGMAC port\u000a\u000appe_xgmac_link_up() masked PPE_XGMAC_TX_FLOW_ENABLE (bit 1) but wrote\u000aPPE_XGMAC_RX_FLOW_ENABLE (bit 0) as the value, so val & mask was always\u000azero and TX pause never enabled on an XGMAC port regardless of what phylink\u000anegotiated. The receive side beside it is correct and is what makes the\u000apair the evidence.\u000a\u000aOnly ports muxed to their XGMAC are affected - the 10G AQR ports on other\u000aboards. Found by inspection; there is no XGMAC port on the bench to run it\u000aon.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "00e31226cd78828080aea53addb208fc7e87f747", "msg" : "qualcommax: qca_ppe: enable TX pause on an XGMAC port", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "c5adfc683037f65b6189e6cf7d2608349860a85f", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: select port 4's PCS for every interface\u000a\u000aThe port 4 arm of the PCS mux assigns its value only for QSGMII and PSGMII\u000aand writes the register on every interface, so an SGMII link - which the\u000adriver advertises for that port - drives the select bit from an\u000auninitialised local. The field names where the port's GMII comes from\u000arather than the protocol carried on it, so one value covers every interface\u000auniphy0 drives.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "c5adfc683037f65b6189e6cf7d2608349860a85f", "msg" : "qualcommax: qca_ppe: select port 4's PCS for every interface", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "8cf2d5cc0c4fa747f5ee993caa0f5d1ea0c7d08f", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: stop advertising RGMII on the SerDes ports\u000a\u000aqca_ppe_phylink_get_caps() adds the four RGMII modes to ports 1 to 4, and\u000athen copies the port's supported interfaces into config->pcs_interfaces, so\u000aphylink is told both the MAC and the PCS carry RGMII there. Neither does.\u000aqca_ppe_mac_link_up() and qca_ppe_mac_link_down() have no RGMII arm and\u000areturn from their default label; the uniphy PCS driver has no RGMII code at\u000aall. Nor can the ports carry it: every board describes these four with a\u000apcs-handle into uniphy0, the SerDes block that driver serves, and\u000appe_pcs_set_mux_hppe() has no arm for ports 1 to 3 while port 4's select\u000anames uniphy0's PCS0 whatever the interface.\u000a\u000aThe failure that leaves is silent. phylink_link_up() calls\u000anetif_carrier_on() whether or not the MAC callback did anything, and\u000amac_link_up() is void, so its early return is not noticed. It returns\u000abefore it opens PPE_PORT_BRIDGE_CTRL_TXMAC_EN, the gate the fabric needs\u000abefore it will hand the port a frame, and before it enables the port's MAC.\u000aA board describing one of these ports as RGMII would read link up at its\u000anegotiated speed and pass no traffic, with no message anywhere. Once the\u000amode is not advertised, phylink_validate() rejects it and\u000aphylink_bringup_phy() fails the port with a warning instead.\u000a\u000aNo qualcommax board describes a PPE port as RGMII: the one rgmii-rxid in\u000athe target's device trees is on a cascaded qca8337's CPU port, whose\u000aPPE-side port is qsgmii. What still reaches a default label after this is\u000athe CPU port's internal link, whose gate qca_ppe_port_enable() opens.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): the four user ports come\u000aup at 1000, 1000, 100 and 1000 Mbit/s full duplex, and forwarding, offload\u000aand dmesg are unchanged.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "8cf2d5cc0c4fa747f5ee993caa0f5d1ea0c7d08f", "msg" : "qualcommax: qca_ppe: stop advertising RGMII on the SerDes ports", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "66344b9be87ed7405ba3a7c963b9488129a2f0f4", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: leave the MAC at gigabit for an unlisted speed\u000a\u000aNeither speed table in qca_ppe_mac_link_up() is exhaustive, and both leave\u000aa speed outside them unhandled: the clock rate is used uninitialised, and\u000appe_xgmac_link_up() returns without writing the speed select while its\u000acaller, which cannot see that it did, goes on to enable the MAC and open\u000athe port's transmit gate.\u000a\u000aDefault both to gigabit.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "66344b9be87ed7405ba3a7c963b9488129a2f0f4", "msg" : "qualcommax: qca_ppe: leave the MAC at gigabit for an unlisted speed", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "245f8d364f2b7d92bb9bc9f0047c1ccd128ceffa", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: leave the loopback port's transmit gate open\u000a\u000appe_mac_hw_init() enables the loopback, waits 100 ms for it and opens that\u000aport's PPE_PORT_BRIDGE_CTRL_TXMAC_EN, the gate the fabric needs before it\u000awill hand a port a frame. Two paths shut it again. qca_ppe_setup() walks\u000aevery port and clears the bit for all but the CPU port, and the loopback\u000aport is described by no board, so DSA also sees it as unused and calls\u000aport_disable() on it. Nothing reopens it: the port has no phylink, so no\u000alink event ever runs, and the loopback probe configured stays unreachable\u000afor the life of the boot.\u000a\u000aGive the bit one owner. ppe_port_bridge_txmac_set() refuses to close the\u000aloopback port's gate, and the setup walk stops writing the bit at all - it\u000awas only ever setting it for the CPU port, whose gate qca_ppe_port_enable()\u000aopens a moment later when DSA enables that port. A user port's gate is\u000astill opened by qca_ppe_mac_link_up() and closed by its link going down.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): PPE_PORT_BRIDGE_CTRL(7)\u000areads 0x0002ff08 before this change and 0x0003ff08 after it, the two\u000adiffering only in TXMAC_EN. The CPU port and the four user ports read the\u000abit set and the two ports no board describes read it clear. Forwarding,\u000aoffload and dmesg are unchanged.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "245f8d364f2b7d92bb9bc9f0047c1ccd128ceffa", "msg" : "qualcommax: qca_ppe: leave the loopback port's transmit gate open", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" ], "commitId" : "5fe599d77f17923235c0d291361c5f164fa9eb67", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_ppe: leave the probe clocks to devres\u000a\u000aThe clocks are prepared and enabled by hand, and every failure after that\u000areturned without disabling them - the ioremap, the regmap, the reset\u000acontrol, the MIB allocation, the per-port clocks and resets, and the switch\u000aregistration all leak the enabled clocks on the way out.\u000a\u000adevm_clk_bulk_get_all_enabled() registers the disable and unprepare with\u000adevres, which is what qca_edma.c beside this driver already uses. The\u000aunwinding, the error label and the two fields the driver kept the bulk in\u000aall go with it.\u000a\u000aFixes: 142104bb90b3 (\"qualcommax: add PPE driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "5fe599d77f17923235c0d291361c5f164fa9eb67", "msg" : "qualcommax: qca_ppe: leave the probe clocks to devres", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe_main.c" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_ppe.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.h", "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "30ef6f840927cd4c44ff7761d794212f967920a5", "timestamp" : 1788980402000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: map every switch queue to the enabled ring\u000a\u000aThe engine has sixteen receive rings and this driver brings up exactly one,\u000athe last. Which ring a frame lands in is chosen by the QID2RID table, which\u000athe driver wrote one word of and left the rest of at whatever the block\u000aresets to. Ring zero, the ring a zeroed id names, is never given a base\u000aaddress and its enable bit is cleared by hardware stop, so any queue whose\u000aid was left at zero points somewhere that cannot deliver.\u000a\u000aFill every word of the table with the ring the per-SoC data names repeated\u000ain each four-bit field, so the value is right whichever field a queue's id\u000aselects. The write is monotone, which is what makes it safe without either\u000athe reset value or the field packing in hand: the enabled ring is the only\u000aplace a frame can be delivered, so a queue that delivers today already\u000aresolves to it and is written the value it already had, and a queue that\u000adoes not is pointing somewhere that cannot deliver. No frame that arrives\u000atoday changes ring.\u000a\u000aThe table's extent is measured; its packing is not. On IPQ8074 words 0 to\u000a63 hold the value the driver writes and the words sampled above them read\u000azero, and word 63 holds an arbitrary 32-bit pattern written to it, so the\u000afill covers the whole table and no bit of a word is hardwired. Which queue\u000aa given word or field serves is not established here, and the fill does not\u000adepend on it.\u000a\u000aWhich of the two queue-to-ring tables actually selects is settled by the\u000adatapath rather than by a reading. PPE_TM_RING_Q_MAP, which the switch side\u000aprograms and which is the only one the kernel's own ppe driver writes -\u000appe_queues_to_ring_init() puts the CPU port's unicast queues on ring zero\u000athere - leaves queue zero on ring zero; QID2RID puts it on the enabled\u000aring; frames arrive. So QID2RID selects, and the switch-side map is\u000adescribing something else for rings this driver never brings up.\u000a\u000aA single id has held this far because the unicast path to the host is queue\u000azero: the CPU port's queue base is zero and its priority map folds all\u000asixteen priorities onto class zero. The CPU port is also given the\u000amulticast queues from 256 up, which is what a flooded frame's copy for the\u000ahost is scheduled through, and the driver has never written ids for them.\u000a\u000aTested on IPQ8074 (Xiaomi AX3600, kernel 6.18.44): every word of the table\u000areads back the enabled ring in all four-bit fields, and the board boots,\u000adials its PPPoE uplink, bridges and forwards offloaded flows on it.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:02 +0200", "id" : "30ef6f840927cd4c44ff7761d794212f967920a5", "msg" : "qualcommax: qca_edma: map every switch queue to the enabled ring", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" }, { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.h" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "f53100d40e1657ced8bce9e3bd0edae1ea5b1d87", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: pad a short frame with its length and its tail\u000a\u000aA frame below the transmit minimum is padded with skb_padto(), which zero\u000a-fills the tailroom and returns without moving the tail, and the length is\u000athen advanced by hand. skb->len therefore runs past the data a head\u000areallocation copies: pskb_expand_head(), three lines below and reached\u000awhenever the frame arrives cloned or short of headroom, copies only as far\u000aas the tail and leaves the pad uninitialised in the new head. The\u000adescriptor still names the padded length, so those bytes go on the wire.\u000a\u000askb_put_padto() advances the tail with the length, which is the whole\u000adifference. It also folds in the length test the call site made, since it\u000ano-ops on a frame that is already long enough.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "f53100d40e1657ced8bce9e3bd0edae1ea5b1d87", "msg" : "qualcommax: qca_edma: pad a short frame with its length and its tail", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "a9adfbf98fb1a39c82e99580e793e76c01d89fa0", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: refuse a frame before its preheader is pushed\u000a\u000aThe transmit routine prepends the 32-byte preheader and only then tests\u000awhether the descriptor's slot still holds an uncompleted frame. A frame\u000arefused there goes back to the qdisc already carrying the preheader, and\u000athe requeue pushes a second one: the descriptor names a length that no\u000alonger describes the frame, and the headroom the push consumed is gone.\u000a\u000aBoth refusals now precede the push, where the ring-full test already sat.\u000aThe slot test depends on nothing between the two points, so the accepted\u000apath is unchanged.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "a9adfbf98fb1a39c82e99580e793e76c01d89fa0", "msg" : "qualcommax: qca_edma: refuse a frame before its preheader is pushed", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "e3c00e95ca170afaa8e95f8a63cd71ca1f65202c", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: free a completed frame with the budget of its caller\u000a\u000aedma_clean_tx() passes its loop bound to napi_consume_skb() as the NAPI\u000abudget. A non-zero budget tells that helper it is running inside a poll and\u000afrees the frame into the per-CPU NAPI cache, which is only safe from\u000asoftirq context. edma_rings_drain() calls the same routine from process\u000acontext with INT_MAX - on an MTU change that alters the receive page order,\u000aand on the probe error and remove paths - so a transmit completion on the\u000asame CPU can interleave with the cache update.\u000a\u000aThe budget the poll was given becomes an argument of its own, zero on the\u000adrain, which routes those frees through dev_consume_skb_any() instead.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "e3c00e95ca170afaa8e95f8a63cd71ca1f65202c", "msg" : "qualcommax: qca_edma: free a completed frame with the budget of its caller", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "f63a9ccd4cc5b4ff30066538924014cad5e5e2b4", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: recheck the transmit ring once it is stopped\u000a\u000aThe queue is stopped from a consumer index read before the descriptor was\u000apublished, and nothing re-reads it afterwards. A completion that drains the\u000aring in that window runs the poll while the queue still reads as running,\u000aso the poll does not wake it, and the stop that follows has no completion\u000aleft behind it: the interface stops transmitting until it is taken down.\u000a\u000anetif_txq_try_stop() carries the barrier and the recheck. The indices the\u000aframe was placed from still decide whether to stop at all, since a consumer\u000aindex only ages into reporting less room than the ring has, so a frame that\u000adoes not fill the ring costs no extra register read.\u000a\u000aA refused frame reaches the same window from the other side. Both\u000aNETDEV_TX_BUSY returns leave a ring the engine is still draining, and the\u000aqueue was stopped by the caller after the transmit lock had been dropped,\u000awith no recheck at all. The refusals stop the queue themselves, under the\u000alock and on the state they were decided from, and the caller no longer\u000atouches the queue state.\u000a\u000aThe two refusals do not name the same resource. A free descriptor count\u000ameasures a full ring, but a taken store slot outlives the descriptor that\u000anamed it: the engine releases a descriptor as soon as it reads it, while\u000aonly the completion clears the slot. A recheck taken from the descriptors\u000aalone restarts the queue on a resource the refused frame still lacks, and\u000athe frame returns to a running queue, which turns the refusal into a retry\u000arather than back pressure. The recheck reports no room while the slot is\u000ataken.\u000a\u000aThe completion side takes the same count against the same threshold\u000athrough __netif_txq_completed_wake(), which carries the barrier the recheck\u000apairs with and reports the completed frames to BQL. That wake is a second\u000awriter of a queue state the control path also stops, so it is held back on\u000aa ring drain, which runs with the queue deliberately stopped and the rings\u000aabout to be freed and is not a poll.\u000a\u000aMeasured on an ipq807x AX3600: three 20 s sixteen-stream transfers through\u000athis ring carry 818, 853 and 824 Mbit/s with no frame dropped on the\u000ainterface, the queue running at the end, every switch port up and the log\u000aclean.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "f63a9ccd4cc5b4ff30066538924014cad5e5e2b4", "msg" : "qualcommax: qca_edma: recheck the transmit ring once it is stopped", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" ], "commitId" : "8cdd105d31ca02fd2c3045a4ede7eeb6ecee3e9d", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: qca_edma: stop the poll before the queue on an MTU change\u000a\u000aA transmit completion wakes a stopped queue, so the poll is the second\u000awriter of the queue state that the MTU change stops. netif_tx_disable()\u000aran first, and a completion landing after it woke the queue and scheduled\u000athe qdisc; napi_disable() then returned as soon as the poll cleared its\u000ascheduled bit, while the poll thread was still inside the local_bh_enable()\u000athat runs the transmit softirq it had queued - against the rings the drain\u000abelow frees.\u000a\u000aPut the poll down first.\u000a\u000aMeasured on an ipq807x AX3600: sixteen mtu changes across the receive page\u000a-order boundary, run under an eight-stream transfer, complete with the\u000atransfer carrying 763 Mbit/s through them, the interface up, every switch\u000aport up and the log clean.\u000a\u000aFixes: bdb0b722b7f0 (\"qualcommax: add EDMA driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "8cdd105d31ca02fd2c3045a4ede7eeb6ecee3e9d", "msg" : "qualcommax: qca_edma: stop the poll before the queue on an MTU change", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/ethernet/qualcomm/qca_edma.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/files/drivers/net/pcs/pcs-qca-uniphy.c" ], "commitId" : "8939d5654a772589b481cf5314b4247773620448", "timestamp" : 1788980403000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: pcs-qca-uniphy: report a USXGMII speed only once the link is up\u000a\u000aqca_uniphy_pcs_get_state_usxgmii() reads the speed out of the USXGMII code\u000aword without consulting the link bit beside it, so a word the partner has\u000anot filled in yet is decoded as a speed and handed to phylink as a resolved\u000alink. The field is read into state->an_complete and never used again.\u000a\u000aReport no link until that bit is set, which is the shape mainline's\u000axpcs_get_state_c73() has for the same word:\u000a\u000a\u0009drivers/net/pcs/pcs-xpcs.c, xpcs_get_state_c73():\u000a\u0009\u0009state->an_complete = xpcs_aneg_done_c73(xpcs, state, ...);\u000a\u0009\u0009if (!state->an_complete) {\u000a\u0009\u0009\u0009state->link = false;\u000a\u0009\u0009\u0009return 0;\u000a\u0009\u0009}\u000a\u000aThis arm needs a USXGMII partner and the bench has no 10G port, so it is\u000anot runtime tested here.\u000a\u000aFixes: 05c180511dda (\"qualcommax: add UNIPHY PCS driver\")\u000aAssisted-by: Claude:claude-opus-5\u000aSigned-off-by: Julius Bairaktaris \u000aLink: https://github.com/openwrt/openwrt/pull/25084\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:00:03 +0200", "id" : "8939d5654a772589b481cf5314b4247773620448", "msg" : "qualcommax: pcs-qca-uniphy: report a USXGMII speed only once the link is up", "paths" : [ { "editType" : "edit", "file" : "target/linux/qualcommax/files/drivers/net/pcs/pcs-qca-uniphy.c" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata", "target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network", "target/linux/qualcommax/ipq50xx/base-files/lib/upgrade/platform.sh", "package/firmware/ipq-wifi/Makefile", "target/linux/qualcommax/ipq50xx/base-files/lib/preinit/09_mount_tp_data", "target/linux/qualcommax/dts/ipq5018-archer-ax55-v1.dts", "target/linux/qualcommax/ipq50xx/base-files/etc/board.d/01_leds", "target/linux/qualcommax/image/ipq50xx.mk", "package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq50xx" ], "commitId" : "8ac63a1c3551fcb3a903ec347e84c1fd1ad6142a", "timestamp" : 1788981383000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "qualcommax: add support for TP-Link Archer AX55 v1\u000a\u000aTP-Link Archer AX55 v1 is an IPQ5018 Wi-Fi 6 router.\u000a\u000aHardware:\u000a SoC: Qualcomm IPQ5018 (dual Cortex-A53)\u000a RAM: 512 MiB\u000a Flash: 128 MiB SPI-NAND (dual firmware slots)\u000a Switch: Realtek RTL8367S (5x GbE), 2.5G HSGMII trunk to gmac1\u000a WiFi: IPQ5018 2.4 GHz + QCN6122 5 GHz (ath11k)\u000a USB: 1x USB 3.0 port, SuperSpeed, using the IPQ5018 SS uni PHY;\u000a the port's 5 V rail is a GPIO-switched regulator wired as the\u000a PHY's vdd-supply, the way the MR5500 does it\u000a Button: Reset, WPS/Wi-Fi\u000a LED: power, LAN, WAN (green/orange), 2.4G, 5G, USB\u000a\u000aAll five front jacks are RTL8367S ports (DSA): blue \"WAN\" = wan,\u000aLAN1-4 = lan1..lan4, over the 2.5G HSGMII trunk.\u000a\u000aThe factory MAC is the \"default-mac\" file in the tp_data UBIFS volume\u000a(there is no raw nvmem cell for it). The volume is attached and mounted\u000aread-only during preinit, so board.d assigns the wired MACs (label MAC\u000afor lan/eth0, +1 for wan) the usual way and the ath11k caldata hotplug\u000aderives the Wi-Fi MACs (+2/+3) from the same mount - the same scheme\u000athe mt7981 archer-ax80-v1 uses for its tp_data. gmac1 has no nvmem MAC\u000asource, so the DSA conduit is pinned to the label MAC in board.d to\u000akeep it stable across boots.\u000a\u000aThe board data files live in firmware_qca-wireless, where they were\u000amerged as f2c37a6b9d1d; this commit pins the ipq-wifi package to that\u000arevision and adds the package entry for the board.\u000a\u000aNote on revisions: some units labelled \"v1\" carry an RTL8367D-family\u000aswitch (chip id 0x6642) instead of the RTL8367S. rtl8365mb cleanly\u000adeclines it (\"unrecognized switch\"), so such a unit boots with no wired\u000aports, and with Wi-Fi off by default it is only reachable via the\u000avendor web recovery (or serial). RTL8367D support in rtl8365mb is being\u000aworked on by others; until it lands the wiki page carries a prominent\u000awarning to identify the switch before flashing. v2/v4 are entirely\u000adifferent hardware and are not covered by this image.\u000a\u000aInstallation (serial console on the JP1 header, 115200 8N1, 1.8 V; note\u000athe RX trace is gapped and must be bridged to type): interrupt U-Boot,\u000aTFTP-boot the initramfs image to 0x44000000, \"bootm\", then \"sysupgrade -n\".\u000aA serial-free path (a telnet-enabled resigned stock image flashed from the\u000avendor web UI, then writing the OpenWrt image to the inactive slot) is\u000adocumented on the device wiki page; that path consumes the\u000ainitramfs-factory.ubi artifact, which is the initramfs kernel wrapped in\u000aa UBI image so it can be written straight into the inactive rootfs\u000apartition with mtd from the running stock firmware.\u000a\u000aRecovery to stock: hold Reset while powering on, set the PC to\u000a192.168.0.10, and upload an official signed TP-Link image at\u000ahttp://192.168.0.1.\u000a\u000aSigned-off-by: Stanislaw Pal \u000a\u000aCo-Authored-By: Claude Opus 5 \u000aLink: https://github.com/openwrt/openwrt/pull/24197\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:16:23 +0200", "id" : "8ac63a1c3551fcb3a903ec347e84c1fd1ad6142a", "msg" : "qualcommax: add support for TP-Link Archer AX55 v1", "paths" : [ { "editType" : "edit", "file" : "package/firmware/ipq-wifi/Makefile" }, { "editType" : "add", "file" : "target/linux/qualcommax/dts/ipq5018-archer-ax55-v1.dts" }, { "editType" : "add", "file" : "target/linux/qualcommax/ipq50xx/base-files/lib/preinit/09_mount_tp_data" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq50xx/base-files/etc/board.d/02_network" }, { "editType" : "edit", "file" : "target/linux/qualcommax/image/ipq50xx.mk" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq50xx/base-files/etc/board.d/01_leds" }, { "editType" : "edit", "file" : "package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq50xx" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata" }, { "editType" : "edit", "file" : "target/linux/qualcommax/ipq50xx/base-files/lib/upgrade/platform.sh" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/generic/config-filter" ], "commitId" : "b886a6ca0c7fd803703650483e36cb04fa13287a", "timestamp" : 1788982597000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "generic: filter: add RUSTC_HAS_SUSPICIOUS_RUNTIME_SYMBOL_DEFINITIONS\u000a\u000aCONFIG_RUSTC_HAS_SUSPICIOUS_RUNTIME_SYMBOL_DEFINITIONS is autodetected\u000abased on rustc version, so filter it out of target configs.\u000a\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:36:37 +0200", "id" : "b886a6ca0c7fd803703650483e36cb04fa13287a", "msg" : "generic: filter: add RUSTC_HAS_SUSPICIOUS_RUNTIME_SYMBOL_DEFINITIONS", "paths" : [ { "editType" : "edit", "file" : "target/linux/generic/config-filter" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/econet/patches-6.18/046-v7.3-net-phy-mediatek-add-EcoNet-EN7528-PHY-support.patch", "target/linux/econet/en7528/config-6.18" ], "commitId" : "6150f5a5ad58efc85073ef53750a58b8f71fb5be", "timestamp" : 1788982781000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "econet: en7528: add support for the EN7528 built-in Ethernet PHYs\u000a\u000aThe EcoNet EN7528 embeds four Gigabit Ethernet PHYs (PHY ID 0x03a29491)\u000abehind its built-in MT7530 switch. Without a driver of their own they\u000afall back to the generic PHY driver, which cannot drive the LED pins of\u000athe PHYs.\u000a\u000aBackport the upstream driver support and enable MEDIATEK_GE_SOC_PHY.\u000aThe PHYs use the same LED register layout as the other SoC PHYs handled\u000aby that driver, but their LED controller powers up with its external\u000acontrol disabled, so the driver enables it from config_init.\u000a\u000aBackported from upstream commit\u000ahttps://github.com/torvalds/linux/commit/b6e2649fff15a17689851b30e5415a3aae2b516e\u000a\u000aSigned-off-by: Ahmed Naseef \u000aLink: https://github.com/openwrt/openwrt/pull/25098\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:39:41 +0200", "id" : "6150f5a5ad58efc85073ef53750a58b8f71fb5be", "msg" : "econet: en7528: add support for the EN7528 built-in Ethernet PHYs", "paths" : [ { "editType" : "edit", "file" : "target/linux/econet/en7528/config-6.18" }, { "editType" : "add", "file" : "target/linux/econet/patches-6.18/046-v7.3-net-phy-mediatek-add-EcoNet-EN7528-PHY-support.patch" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "target/linux/econet/dts/en7528_dasan_h660gm-a.dtsi", "target/linux/econet/dts/en7528_dasan_h660gm-a-generic.dts", "target/linux/econet/dts/en7528_jiofiber_jcow414.dts", "target/linux/econet/dts/en7528.dtsi", "target/linux/econet/dts/en7528_jiofiber.dtsi", "target/linux/econet/dts/en7528_dasan_h660gm-a-airtel.dts", "target/linux/econet/base-files/etc/board.d/01_leds", "target/linux/econet/dts/en7528_jiofiber_jcow407.dts" ], "commitId" : "f3614686abca9e37249c9203822858a5cdbef8ce", "timestamp" : 1788982781000, "author" : { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, "authorEmail" : "robimarko@gmail.com", "comment" : "econet: en7528: offload the LAN LEDs to the built-in GPHYs\u000a\u000aThe LAN LEDs of the EN7528 boards are wired to the LED pins of the GPHYs\u000asitting behind the switch ports, but were described as plain GPIOs, so\u000athey were left under software control and stayed dark.\u000a\u000aAdd the LED nodes to the GPHYs of the SoC .dtsi, mux the LED pins to the\u000amatching phyN_ledM function of the pin controller, and replace the\u000agpio-leds nodes of the LAN LEDs with references to the PHY LEDs. The\u000aLEDs are then driven by the PHY itself, without any CPU involvement.\u000a\u000aThe JioFiber boards have both LED pins of every GPHY wired up, giving a\u000abicolour LED per socket. The H660GM-A boards only have the LED1 pins\u000awired, as the LED0 pins are used as GPIOs for the other LEDs and for the\u000aWPS button; the amber LEDs of the generic variant stay plain GPIOs.\u000a\u000aAdd board.d/01_leds to hook the LEDs up to the netdev trigger, which the\u000aPHY driver offloads to the hardware.\u000a\u000aSigned-off-by: Ahmed Naseef \u000aLink: https://github.com/openwrt/openwrt/pull/25098\u000aSigned-off-by: Robert Marko \u000a", "date" : "2026-09-09 21:39:41 +0200", "id" : "f3614686abca9e37249c9203822858a5cdbef8ce", "msg" : "econet: en7528: offload the LAN LEDs to the built-in GPHYs", "paths" : [ { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a-generic.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528.dtsi" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber_jcow414.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber.dtsi" }, { "editType" : "add", "file" : "target/linux/econet/base-files/etc/board.d/01_leds" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a-airtel.dts" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_dasan_h660gm-a.dtsi" }, { "editType" : "edit", "file" : "target/linux/econet/dts/en7528_jiofiber_jcow407.dts" } ] } ], "kind" : "git" }, "culprits" : [ { "absoluteUrl" : "https://taiha.net/jenkins/user/jonas", "fullName" : "jonas" }, { "absoluteUrl" : "https://taiha.net/jenkins/user/markus.stockhausen", "fullName" : "markus.stockhausen" }, { "absoluteUrl" : "https://taiha.net/jenkins/user/robimarko", "fullName" : "robimarko" }, { "absoluteUrl" : "https://taiha.net/jenkins/user/daniel", "fullName" : "daniel" } ] }