realtek: dsa: rtl839x: fix uninitialized global access
Setup for DSA QOS on RTL839x accesses unitialized memory. For some reason the handover of the priv structure was realized via global intermediate variable switch_priv. During refactoring for adbb9a6 ("realtek: dsa: rtl83xx: fix init section mismatch") this was not noticed. Since then RTL839x devices crash during startup.
Fix this by using standard handover via function parameters.
Fixes: adbb9a6 ("realtek: dsa: rtl83xx: fix init section mismatch") Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21703 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: ac96463)
Signed-off-by: Peter Meiser <peter.meiser@gmx.com> Link: https://github.com/openwrt/openwrt/pull/19737 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 168d5af)
qualcommax: ipq807x: fix sysupgrade for TCL LINKHUB HH500V
Fix missing reference to bootconfig.sh that was breaking root partition swap.
Signed-off-by: Milan Krstic <milan.krstic@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21721 Signed-off-by: Robert Marko <robert.marko@sartura.hr> (commit: 30378ff)
The ethernet driver uses an indirection for access to the MAC_PORT_CTRL register (aka. MAC_L2_PORT_CTRL on RTL93xx). It defines the base address and adds up the cpu port offset. This is not needed as the driver does not handle the non-cpu ports. Use direct register access instead and avoid register confusion by always using the "_L2_" naming.
While we are here:
- Drop the functions and use defines instead - Add CPU port defines for better readability
As there are actually 2 versions of the GS1900-24 where the only difference is the amount of ram, use a common dtsi and make the original A1 model dts include the dtsi and only override the memory size.
* If "Active Image" has the first option selected, OpenWrt will need to be flashed to the "Active" partition. If the second option is selected, OpenWrt will need to be flashed to the "Backup" partition.
* Navigate to Maintenance > Firmware > Upload
* Upload the openwrt-realtek-rtl838x-zyxel_gs1900-24-b1-initramfs-kernel.bin file by your preferred method to the previously determined partition. When prompted, select to boot from the newly flashed image, and reboot the switch.
* Once OpenWrt has booted, scp the sysupgrade image to /tmp and flash it:
* Configure your client with a static 192.168.1.x IP (e.g. 192.168.1.10).
* Set up a TFTP server on your client and make it serve the initramfs image.
* Connect serial, power up the switch, interrupt U-boot by hitting the space bar, and enable the network:
> rtk network on
> Since the GS1900-24 B1 is a dual-partition device, you want to keep the OEM firmware on the backup partition for the time being. OpenWrt can only be installed in the first partition anyway (hardcoded in the DTS). To ensure we are set to boot from the first partition, issue the following commands:
> setsys bootpartition 0 > savesys
* Download the image onto the device and boot from it:
The symbol error reset function misses the default sequence. E.g. kernel spits the message "rtpcs_930x_sds_sym_err_reset unsupported phy mode" when working on 2500base-x.
Align the function with the SDK by
- adding QSGMII mode - adding the "all other modes" switch - working with "channels" to make clearer what happens
Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/21718 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 81f6eca)
realtek: pcs: rtl931x: use SerDes hw mode for CMU setup
Switch the CMU setup functions to use the SerDes hardware mode instead of the PHY interface mode.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21707 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: a477315)
realtek: pcs: rtl931x: fix and cleanup CMU functions
Fix the wrong values bit values when setting CMU band which were the same for both 'enable == true' and 'enable == false'.
While at it, fix some coding issues in the CMU functions: - drop confusing debug output - use ternary value instead of if-else - return proper error - make variable declaration in reverse christmas tree - drop unneeded temporary value
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21707 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 48ada31)
The implementations for CMU management for RTL930x and RTL931x differ in their terminology but not that much in their technical aspect. For both it seems to be the case that two adjacent SerDes share a CMU. This CMU contains a ring PLL for low speeds (capable of 1G/2.5G) and an LC PLL for high speeds (capable of 1G/2.5G/10G).
Introduce an enum for the PLL type, used for both RTL93xx variants. Align the naming of internal variables, especially in the RTL931x implementation. Rename cmu_type to pll_type because this is much more accurate. Use 'force_' instead of 'frc_' to make clear what it means. Also rename the function from 'cmu_type_set' to 'config_cmu' because it obviously does more than just setting the CMU type but rather configures the CMU.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21707 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 638ccb6)
The RTL931X CMU code was only capable of setting up ring PLL. This is fine so far as most modes use this PLL type. Other modes are not handled by the code, neither here nor in the SDK. Though, the SDK has the needed sequence to setup the LC PLL. Using LC PLL seems to be handled somewhere else.
Include the small sequence from the SDK to have it, though not used yet. This could be helpful for further development which goes beyond the SDK.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21707 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 180f53d)
This update contains the following upstream fixes: f75b9d2c9f5b wifi: rtl8xxxu: Add USB ID 2001:3328 for D-Link AN3U rev. A1 401b10a72f5a wifi: rtw88: Add USB ID 2001:3329 for D-Link AC13U rev. A1 c0d93d69e147 staging: rtl8723bs: fix out-of-bounds read in rtw_get_ie() parser e841d8ea7223 staging: rtl8723bs: fix stack buffer overflow in OnAssocReq IE parsing bf323db1d883 staging: rtl8723bs: fix out-of-bounds read in OnBeacon ESR IE parsing b1497ea24639 wifi: ath10k: move recovery check logic into a new work 99fc0689a588 wifi: ath11k: restore register window after global reset ab0554f51e5f wifi: ath12k: Fix MSDU buffer types handling in RX error path d911fa97dab3 wifi: ath12k: fix VHT MCS assignment ca2a33cee1ef wifi: ath12k: fix TX and RX MCS rate configurations in HE mode 18d4706956b7 wifi: ath11k: fix VHT MCS assignment 6b1a0da75932 wifi: ath11k: fix peer HE MCS assignment d0a5b5d56438 wifi: ath12k: restore register window after global reset 1564c04afa92 wifi: iwlwifi: mld: add null check for kzalloc() in iwl_mld_send_proto_offload() d0bb3db7b295 wifi: ath12k: fix potential memory leak in ath12k_wow_arp_ns_offload() 36faecac7a2c wifi: ath12k: fix reusing m3 memory 4f93750fa588 wifi: ath12k: fix error handling in creating hardware group 41b623129175 wifi: ath12k: enforce vdev limit in ath12k_mac_vdev_create() e442e820e953 wifi: ath12k: unassign arvif on scan vdev create failure bcf44fe565bf wifi: rtw89: usb: use common error path for skbs in rtw89_usb_rx_handler() 87cc6fe79c3e wifi: rtw89: usb: fix leak in rtw89_usb_write_port() c7ca777c5879 wifi: ath12k: Fix timeout error during beacon stats retrieval 51b823d7723f wifi: cw1200: Fix potential memory leak in cw1200_bh_rx_helper() c9d1c4152e6d wifi: rtl818x: Fix potential memory leaks in rtl8180_init_rx_ring() a6fb8785b179 wifi: mac80211: fix CMAC functions not handling errors 5ebf0fe7eaef wifi: rtl818x: rtl8187: Fix potential buffer underflow in rtl8187_rx_cb() b8f34c1c5c4f wifi: mt76: mt7996: fix null pointer deref in mt7996_conf_tx() cbeca0b7ea20 wifi: mt76: mt7996: Remove unnecessary link_id checks in mt7996_tx d582d0e988d6 wifi: mt76: wed: use proper wed reference in mt76 wed driver callabacks d2d11298dfc3 wifi: mt76: mt7996: Remove useless check in mt7996_msdu_page_get_from_cache() 2cde732373a7 Revert "wifi: mt76: mt792x: improve monitor interface handling" 74bb080717a3 wifi: mt76: mt7996: fix max nss value when getting rx chainmask 95bb36f8d6b3 wifi: mt76: mt7996: fix implicit beamforming support for mt7992 ee94375d06b5 wifi: mt76: mt7996: fix several fields in mt7996_mcu_bss_basic_tlv() d64e6f27260e wifi: mt76: mt7996: fix teardown command for an MLD peer e5c42efeb162 wifi: mt76: mt7996: set link_valid field when initializing wcid 9a43ed9ab800 wifi: mt76: mt7996: fix MLD group index assignment 7d6cd8f51ad8 wifi: mt76: mt7996: fix MLO set key and group key issues 1a4b481a21ae wifi: mt76: mt7996: fix using wrong phy to start in mt7996_mac_restart() b4b789d24319 wifi: mt76: mt7996: fix EMI rings for RRO 46f0648e261c wifi: mt76: mt7996: grab mt76 mutex in mt7996_mac_sta_event() 70656b45467c wifi: mt76: Move mt76_abort_scan out of mt76_reset_device() c319967690d4 wifi: mt76: mt7996: skip deflink accounting for offchannel links abdedd46dc58 wifi: mt76: mt7996: skip ieee80211_iter_keys() on scanning link remove f4c57afff3b0 wifi: mt76: mt7996: Add missing locking in mt7996_mac_sta_rc_work() 4d42aba0ee49 mt76: mt7615: Fix memory leak in mt7615_mcu_wtbl_sta_add() ad26a7ef0488 wifi: ieee80211: correct FILS status codes 40257a2ef1bc wifi: rtl8xxxu: Fix HT40 channel config for RTL8192CU, RTL8723AU c3ab9657866f wifi: cfg80211: stop radar detection in cfg80211_leave() 0283fac52b42 wifi: cfg80211: use cfg80211_leave() in iftype change 9c6f9b2a80ed wifi: mt76: mt792x: fix wifi init fail by setting MCU_RUNNING after CLC load f5323b43019d wifi: brcmfmac: Add DMI nvram filename quirk for Acer A1 840 tablet 498e286941b9 wifi: mt76: Fix DTS power-limits on little endian systems e5c129a05531 wifi: rtw88: limit indirect IO under powered off for RTL8822CS 90a15ff32464 wifi: rtlwifi: 8192cu: fix tid out of range in rtl92cu_tx_fill_desc() 7ea38152a289 wifi: cfg80211: sme: store capped length in __cfg80211_connect_result() 182a2786d248 wifi: mac80211: do not use old MBSSID elements de5eb6b65e9f wifi: iwlwifi: Fix firmware version handling a21704df4024 wifi: mac80211: Discard Beacon frames to non-broadcast address e3c35177103e wifi: avoid kernel-infoleak from struct iw_point b97be67dc06e wifi: mac80211: restore non-chanctx injection behaviour 1251bbdb8f5b wifi: mac80211_hwsim: fix typo in frequency notification
The following patches were applied upstream: build/130-backports-move-__counted_by-to-compiler_types.h-head.patch patch [1] build/999-kernel-6.12.64.patch [2]
wifi-scripts: fix ucode mobility_domain default value
The mobility_domain value generated by ucode differed from the previous shell script implementation. The legacy shell script used `echo` on the SSID, which appended a trailing newline.
To maintain roaming compatibility with pre-25.12 releases and OpenWrt forks in default configuration, update the ucode logic to include this newline character when generating the default value.
- It uses register 29 (write only companion of ext. page register 30) - "configuration" only reads registers 2/3 and writes a message - "configuration" is run during probing
Drop the useless coding. As this was the last consumer drop register 29 define too.
XikeStor SKS8300-8T is a 8 ports Multi-Gig switch, based on the RTL9303.
Specifications:
- SoC : Realtek RTL9303 - RAM : DDR3 512 MiB - Flash : SPI-NOR 32 MiB (Macronix) - CPU : 800MHz - Ethernet : 8× 1G/2.5G/5G/10G Base-T RJ45 ports (RTL8261N) - Keys (GPIO) : 1x - UART : "Console" port on the front panel - type : RS-232C - connector : RJ-45 - settings : 115200 8N1 - Power : 12 VDC, 4A - Temperature sensor : LM75 or compatible - Fan controller : SensyLink CTF2302
Flash instruction using initramfs image:
1. Prepare TFTP server & connect to serial port. 2. Connect your computer to one of the RJ45 ports on SKS8300-8T 3. Power on SKS8300-8T and interrupt autoboot with Shift + A. 4. Use Shift + Q to drop from vendor CLI to U-Boot CLI. 5. Set the boot command to enable network on boot. > setenv bootcmd 'mw.l 0x8401da94 0; rtk network on; boota' 6. Set switch IP and TFTP server IP (optional, adjust to your setup). > setenv ipaddr <ip> > setenv serverip <ip> 7. Download initramfs image from TFTP server. > tftpboot 0x83000000 <image name> 8. Boot with the downloaded image. > bootm 0x83000000 9. With rambooted OpenWrt, backup the stock firmware if needed. 10. Copy sysupgrade image to the device. 11. Perform sysupgrade with the sysupgrade image. 12. After reboot, you should have functional OpenWrt.
In OpenWrt, it is necessary to execute "rtk network on" to enable full networking functionality. However, the internal U-Boot initialization (which shares logic with "rtk network init" initializing MAC only and configures the fan controller) sets a flag at memory address 0x8401da94. Once this flag is set, any subsequent calls to "rtk network on" are blocked. To bypass this, resetting 0x8401da94 to 0 by step 5, ensuring that the network can be properly initialized later. This specific address was confirmed in U-Boot 2011.12.(3.6.11.55242) (Jan 06 2025 - 14:39:46) by decompiling the function that references the "rtk_mac_init" string.
Reverting to stock firmware:
1. Connect to serial port. 2. Power on SKS8300-8T and interrupt autoboot with Shift + A. 3. Use Shift + Q to drop from vendor CLI to U-Boot CLI. 4. Set the boot command to the firmware default. > setenv bootcmd boota 5. Enable network. > rtk network on 6. Boot OpenWrt. > boota 7. Download latest firmware from XikeStor and upload to your device. 8. Write firmware with 'sysupgrade -F'. 9. After reboot, stock firmware should boot automatically.
This commit adds support for Hasivo S1100WP-8GT-SE switch.
Device specification -------------------- SoC Type: Realtek RTL9303 RAM: Samsung K4B2G1646F-BYMA (256MB DDR3 SDRAM) Flash: Fudan FM25Q128A (16 MB) Ethernet: 8x RTL8221B 10/100/1000/2500Mbps PHY LEDs: 2 LEDs + 4 LEDs/port 1x power green (no control) 1x system green (via RLT9303 GPIO) 3x RJ45 LEDs/port (via HC595 shift registers on LED spi) 1x Green 1x Green/Orange 1x Orange LED/port for PoE status (below RJ45, on STC8) Button: Reset USB ports: None Bootloader: Realtek U-Boot 2011.12.(3.6.6.55087) (Nov 13 2022 - 14:37:31) Fan: None installed (but board provision for temp/FET/fan) POE: 2x HS104PTI for 802.3af/at/bt PoE (Not yet working)
Installing OpenWrt ------------------ 1. UART RJ45 requires soldering a connector to the empty footprint (RJ1). (Amphenol RJHSEE380 or similar) 2. Connect to UART 38400@8n1, using Cisco Console Rollover cable (RS232) 3. Set computer IP to 192.168.0.111, and plug in with 2.5Gbps 4. Enter bootloader by pressing esc key during boot 5. Enter password `Hs2021cfgmg` 6. Type `XXXX` to get into U-Boot 7. Type `rtk network on` 8. Use tftp if you have a 2.5G link (other speeds won't work). If serial, you can increase baudrate in uboot with `setenv baudrate 115200` 9.1. `tftpboot 0x84f00000 <openwrt-initramfs-filename>` 9.2. Otherwise use serial transfer (Y modem): `loady 0x84f00000` 10. `bootm 0x84f00000`
Now you should be in OpenWRT, and can use sysupgrade to install.
The gemini is using split squashfs/jffs2 root filesystems on all devices, so without CONFIG_BLK_DEV_LOOP the device does not gain a writeable root filesystem with these boot messages:
mount_root: unable to create loop device mount_root: jffs2 not ready yet, using temporary tmpfs overlay
and then it never gets out of that. Fix this so we get writeable rootfs again.
mvebu: cortex-a53: fix Methode eDPU migration to upstream DTS
Migration of the eDPU DTS to upstream one broke the eDPU plus model since the required ethernet aliases are missing and U-Boot then cannot find the required ethernet nodes.
So, after sending the required fix upstream, lets apply it in OpenWrt as well.
Fixes: 9852dda4105c ("mvebu: move DTS diff into a patch for Methode uDPU") Signed-off-by: Robert Marko <robert.marko@sartura.hr> (commit: 3353827)
Add IPQ Wifi entry for ath79 TP-Link TL-WA1201 v2.
Signed-off-by: Christoph Krapp <achterin@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21736 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 0230a35)
ath79: add calibration variant for TP-Link TL-WA1201 v2
Now that we have a board file, add calibration variant for TP-Link TL-WA1201 v2 and add ipq-wifi package for it.
Tested-by: Jim McDonald <122668301+jimmyd998@users.noreply.github.com> Signed-off-by: Christoph Krapp <achterin@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21736 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 0fa94cf)
The ixp4xx is using split squashfs/jffs2 root filesystems on some devices, so without CONFIG_BLK_DEV_LOOP the device does not gain a writeable root filesystem with these boot messages:
mount_root: unable to create loop device mount_root: jffs2 not ready yet, using temporary tmpfs overlay
and then it never gets out of that. Fix this so we get writeable rootfs again.
Add a dedicated structure for SerDes operations. This will be used for several common operations currently called individually in various places of the code.
Start with defining the basic read and write operations for a SerDes in this structure. Use generic implementations of these operations for all variants (RTL83xx, RTL93xx) for now.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21592 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 136cec0)
realtek: rtl930x: move SerDes mapping from MDIO to PCS
For RTL930x, the SerDes MDIO driver performed a slight SerDes ID mapping on certain conditions. Instead of keeping this mapping in the MDIO and try to extend it for further quirks, lets just be a plain MDIO here and let the user (PCS) deal with these complex quirks.
Drop the mapping from the SerDes MDIO driver and move it to the PCS driver by leveraging the previously introduced SerDes operations structure. Define separate ops which incorporate this mapping and use those instead of the generic implementations.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21592 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 0a1e101)
There is some special logic used for certain writes to digital pages for RTL93xx SerDes, especially when configuring the XSGMII mode. For RTL930x this applies to SerDes 2 and 3, for RTL93xx to more. In this case, a dual-read/write to SDS and SDS + 1 is done. While the corresponding mapping from front to back SDS for RTL931x is currently covered in the SerDes MDIO driver, it isn't for RTL930x.
To cover these special cases and provide a clear interface on that, introduce an XSG write SerDes operation. All these dual-read/write cases can be expressed with such an XSG operation whose internal semantics are defined for each switchcore family.
This could be done just with plain dual read/write calls however this isn't a clean approach and may be confusing while comparing our functionality with the SDK, especially for RTL930x.
In practice, if this isn't handled correctly, only half of the ports of an XSGMII-connected RTL8218D do work because some required values aren't applied for the background SerDes 3.
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com> Link: https://github.com/openwrt/openwrt/pull/21592 Signed-off-by: Robert Marko <robimarko@gmail.com> (commit: 6879c8e)
Vulnerabilities fixed: CVE-2025-11961 and CVE-2025-11964 Various improvements and bug fixes. Changelog: https://github.com/the-tcpdump-group/libpcap/blob/libpcap-1.10.6/CHANGES
